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A novel dualband impedance transformer based on fractional-order inductor and capacitor is proposed in this paper. This transformer is designed to transfer the arbitrary frequency-dependent complex impedances sources to loads at two irrelevant frequencies with one fractional-order inductor and two fractional-order capacitors. Each fractional-order element has two parameters to be determined: the order...
A current mode background light subtraction circuit is presented for time-of-flight based 3D cameras. The circuit is implemented in current mode to overcome the requirement of large size MIM capacitors in voltage domain. The current based subtraction also increases the camera speed due to reduction of two integration cycles as compared to voltage mode circuits. A current integrator circuit is used...
A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-amplifier stage) is limited to Vdd/2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above Vdd/2. As a result, during the comparison the second stage...
This paper proposed a random chopper (RC) architecture for use in a capacitive accelerometer readout circuit. This technique randomizes low-frequency flicker noise to be more thermal-noise-like, and also boosts the small signal charges due to acceleration. The noise-equivalent acceleration (NEA) of the proposed RC readout circuit is greatly reduced compared with conventional correlated double sampling...
This paper proposes a pipelined time stretching technique for high throughput counter-based time-to-digital converters (TDC). Time stretching technique is used to increase the resolution of counter-based TDCs, yet it carries an inherent weakness of having a long conversion time due to the stretching phase. Without significant increment of chip area, the proposed pipelined time stretching method is...
This paper describes a CMOS 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) using TCC(Threshold Configuring Comparator) for the 5 MSBs. This architecture enables SAR to simplify C-DAC and reduce power consumption. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 750um × 700um. It consumes 53uW and achieves an ENOB of 9.7 bits at sampling...
Integrated voltage regulators (IVRs) fabricated and positioned close to the microprocessors can improve the energy conversion efficiency, power density and the output voltage regulation performance compared to discrete VRs. The highest cost in terms of space and volume in such IVRs corresponds to the bulky passive components needed for their operation. In this paper, two different hybrid architectures...
A synchronous variable reluctance machine (VRM) can work with either a grid connection or a capacitor bank, each would need to provide the machine with positive reactive power to counter the machine inductive coils. Simulation shows that synchronous Variable capacitance could improve the VRM power transfer, when working both as a generator and as a motor. A 3∼synchronous VRM was modelled and simulated...
Series of commissioning tests are needed before UHV transmission system putting into operation. In this paper, with the characteristics of Huainan-Shanghai 1000kV transmission system, electromagnetic transient simulation results and experimental data portion commissioning tests were compared and analyzed. Three typical experiments were studied, including the switching capacitor of low-voltage side...
This paper presents a new type of cascaded PWM ac-ac converter with phase-shift PWM control. It can reach high output voltage by cascading single-phase units of low voltage rating devices. The proposed converter does not sense current/voltage polarity, and does not require current/voltage sensors and lossy snubbers for commutation, thereby the control complexity can be decreased. It has no shoot-through...
In this paper, a modulation strategy based on zero-sequence voltage injection is proposed for module multilevel converter (MMC). By the proposed method, the remaining capacitor voltages not vary and the line-to-line voltages are balanced. This method is easy to be implemented by adjusting the voltage injection coefficient when SM fault occurs. The coefficient of injected zero-sequence voltage is designed...
The concept of HVDC taps drawing small amount of power from HVDC lines to the rural places has been considered for several decades. Most of the earlier tap converters were limited by its loss, cost, reliability, and control difficulties. However, in this paper, the emerging modular multilevel converter (MMC) is adopted as the series HVDC tap, which reveals significantly improved performance and feasibility...
A new galvanically isolated DC-DC converter has been presented in this paper. The proposed topology is based on the quasi-switched-boost impedance network. It not only includes all positive characteristics of previous converters including continuous input current, high boost ability and high efficiency, but also has the prominent features of less passive elements utilization, small size and light...
This paper presents high-power-density inverter with pulse current injection power decoupling method. In order to reduce the dc-link capacitor significantly, dc-link current is fully analyzed with double Fourier method in theory. Compared with the traditional 2nd harmonic power decoupling method, the pulse current injection method considers not only 2nd order harmonic but also the higher order harmonics...
A low power switching method for SAR ADC is proposed in this paper. With this switching method the comparator first compares the sampled input voltage with Vref/2 to generate the MSB and determine whether to use Vref/2 or Vref as the comparator reference voltage in the following conversation steps, and the DAC with a split capacitor array uses Vref/2 as the reference voltage to generate the remaining...
The paper aims at various techniques to approximate fractional capacitor using passive elements. The fractional capacitors have been used to implement an astable multivibrator, sinusoidal oscillator, function generator and filters. PSPICE simulation results have been shown for the circuits both with and without using the fractional capacitors. By comparing the simulation results, it can be shown that...
In most substation protection studies, capacitor bank parameters are derived from manufacturer nameplate values. However, the actual parameters could be different from the nominal rating as a result of manufacturing variance, assembling, material aging, and temperature dependencies. Wide manufacturing tolerance could lead to non-negligible calculation inaccuracy that affecting successive studies....
This paper develops an integrated multi-domain simulation tool for distribution systems designed specifically for applications in wind power analysis. The proposed tool consists of steady-state, electromechanical transient, and electromagnetic transient models of voltage sources, transmission lines, transformers, capacitor banks, fixed-speed wind turbines (FSWTs), and wide-slip wind turbines (WSWTs)...
A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-µm CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (VDD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the...
A power management control method is proposed for the three-phase-to-single-phase matrix converter (MC)-based solid state transformer (SST) linking two grids. The MC-SST presents low weight and high controllability with respect to a conventional line-frequency transformer. Moreover, the single-stage ac-ac power conversion and compact volume are achieved compared to a three-stage SST, owing to the...
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