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This paper describes a comparative study of comparator and encoder in 4-bit Flash Analog to Digital Converter (ADC) for Pipeline ADC to obtain a high speed ADC. In this paper, the conventional comparator is replaced with an open loop comparator and the non-ROM type encoder is used as the alternative for the conventional encoder. It is implemented using 0.18μm CMOS technology. Generally, the Silvaco...
This paper presents the comparison between multistage amplifier and folded cascode amplifier design using 0.18μm CMOS technology. The objective of this project is to compare gain and power dissipation between these two design models. Sample and hold circuit (SHC) is the main component in pipelined ADC. Designing a low power, high gain SHC is crucial, that is the main reason why multistage amplifier...
In this paper, a the digitally programmable current amplifier (DP-CA) for NMOS integrated circuit implementation is presented. To provide precise digital control of the gain characteristic, the proposed DP-CA comprises current proportional gain blocks that can be digitally controlled. The proposed DP-CA can be operated from a low power supply of ±1.25V. As an application example of the proposed circuit,...
A track-and-hold amplifier (THA) for 1GSps 8bit pipelined folding and interpolation (F&I) ADC is realized in TSMC 0.18 µm 1p6m CMOS process. The THA adopts bootstrapped switch instead of simple MOS switch. Dummy transistors and duplicated source follower are also taken to improve its performance. Post simulation results prove that the THA achieves a SNDR of 51.1dB at Nyquist sampling rate. Under...
In this paper, a CMOS monolithic digitized light transducer with calibration circuits for ambient light sensor applications is newly proposed. The proposed chip is attractive due to the fact that analog processing circuits and light sensor arrays are integrated robustly and compactly. The output signal of the proposed light transducer is a pulse stream, it could be easily sent over a wide range of...
This paper presents a broadband bandpass amplifier in CMOS technology based on the cascaded single-stage distributed amplifier (CSSDA) technique. In this design, the conventional lowpass LC filter structure of the CMOS CSSDA is replaced by a bandpass LC filter structure lines. The CSSDA has a nearly constant gain, linear phase response, and acceptable return loss in the passband. Simulation results...
Mixer is one of the main modules of a transmitter system, and its performance will heavily impact the functionality of the entire transmitter. Gilbert cell structure can achieve high degree of RF (Radio Frequency) and LO (Local Oscillator) isolation, thus loosening filtering output requirements. This paper presents a up-conversion mixer, designed in a standard TSMC0.13 μm CMOS technology, for 1.8–2...
This paper presents a new structure of variable gain amplifier (VGA) in which a modified Gilbert Cell is firstly proposed to implement a low power wide dynamic range VGA. The proposed VGA can provide 50-dB dynamic range within a linear error of 1-dB. Furthermore, the proposed circuit consumes less than 0.5-mA current and occupies about only 0.12-mm2 chip area, both of which are relatively low in terms...
In this paper, a two-stage cascode class F power amplifier (PA) intended for class 1 Bluetooth application is presented using standard 0.18-μm CMOS technology. In the proposed PA, a cascode schematic is used not only to avoid from overflow current but also to have a good isolation. Furthermore, the class F power amplifier is designed to improve the power efficiency using the operating mode in either...
This paper presents a MOS translinear principle based current mode CMOS four-quadrant multiplier. The multiplication is implemented by two MOS translinear loops working in the subthreshold region. The remainder of the differential output currents is the multiplication of the signals carried by the differential input currents. The multiplier characterized with a high bandwidth and low power consumption...
This paper presents the design of an operational transconductance amplifier-C (OTA-C) low pass filter for a portable electrocardiogram (ECG) detection system. A fifth-order Butterworth using ladder topology is utilized to reduce the effect of component tolerance and to provide a maximally flat response. The proposed filter is based on a novel class AB digitally programmable fully differential OTA...
This paper presents a power line communications (PLC) receiver in ICs with emphasis on robustness. The PLC receiver intends to control internal logic values of ICs through power pins. It employs a differential Schmitt trigger to increase noise immunity and tolerate supply voltage fluctuations. The receiver is designed and laid out in 0.18 µm CMOS technology. Post-layout simulation results show that...
A novel CMOS current mode analog multiplier is presented. The design is based on using MOSFET operating in subthreshold region to achieve ultra low power dissipation. The circuit is operated from ± 0.75V DC supply. The proposed circuit has been simulated using Tanner in 0.35µm TSMC CMOS process. Simulation results show that the total power dissipation is 2.3µW, total harmonic distortion is 0.7% ,...
This paper presents a new electronically tunable voltage-mode quadrature sinusoidal oscillator employing four single-ended operational transconductance amplifiers (OTAs) and two grounded capacitors. In general, the single-ended OTA configuration is simpler than the multiple-output OTA counterpart and the requirement of grounded capacitors is preferable for an integrated circuit fabrication process...
In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average...
In a classical video monitoring system, though for most of the time the captured images contain no relevant information, it cannot prevent the monitoring system from useless power consuming for image processing. To improve this, one technique proved to be effective for a video monitoring system to reduce its power consumption is based on macro-pixels or blocks of pixels for region of interest (ROI)...
A 6–10GHz 0.8V supply voltage low power consumption mixer for ultra-wideband (UWB) application is presented in this paper. The proposed mixer is based on a folded structure for the purpose of low supply voltage. Sub-harmonic technique is adopted to reduce LO signal frequency and suppress LO leakage signal which might appear in the input RF ports. The bias points of RF input stages are selected to...
This paper presents a design of an ultra-low power UWB transmitter based on 4th and 5th derivative Gaussian pulse shapes implemented in UMC 90nm CMOS technology. The simulations show 119mV peak to peak pulse amplitude and the pulse width of 240 ps for the 5th derivative Gaussian pulse and 99.71mV pulse amplitude and 190 ps pulse width for the 4th derivative Gaussian pulse. Power consumption of the...
A 4-transistor (4-T) CMOS voltage reference with two high PSRR output voltages is presented. The output voltages are equal to the scaled voltage difference of two threshold voltages at absolute zero temperature. The temperature coefficients' (TCs) difference of the two threshold voltages is compensated by another transistor-size-controlled temperature coefficient to achieve zero TC outputs. A CMOS...
We propose a multi-segment approximation method to design a CMOS current-mode hyperbolic tangent sigmoid function with high accuracy and wide input dynamic range. The dynamic range is dependent on the number of segments and the accuracy is related to the dividing point. From mathematical results, we can observe the proposed method outperforms traditional methods. We implement the multi-segment approximation...
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