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The de-synchronization methodology, which directly converts a synchronous circuit into an asynchronous counterpart according to the physical structure of pipelines, is very popular for its simplicity. However, the simplicity of the design methodology also introduces some power redundancy and performance reduction to de-synchronized circuits. This paper firstly investigates the influence of actual...
In today's Traffic Flow Management (TFM) operation, some flow restrictions may be used that are procedurally applied to aircraft while they are on the ground before departure. Although there are some drawbacks to this approach, the application of required delay before flights depart allows that delay to be taken by the flight when it does not have to burn fuel to stay aloft. Delaying flights on the...
Heterogeneous long term evolution (LTE) networks evolve as a possible solution to accommodate the exponential growth of mobile data. However, the heterogeneity introduces several design challenges such as increasing interference and mobility overhead. In this paper, we propose Extended Synchronization Signals (ESS) to eliminate the unavoidable physical cell identity (PCI) confusion problem in dense...
We present a low overhead technique that can be used to offset both large systematic and random process delay variation in the near-threshold voltage operation region. We present an analysis of this this technique applied to a 65nm CMOS self synchronous FPGA that is capable of operation from 2.0V to 0.37V. By using dual voltage supplies, we can offset gate-level pipeline stages that show large delay...
We present a highly available system for environments such as stock trading, where high request rates and low latency requirements dictate that service disruption on the order of seconds in length can be unacceptable. After a node failure, our system avoids delays in processing due to detecting the failure or transferring control to a back-up node. We achieve this by using multiple primary nodes which...
Ethernet is a popular technology for industrial networking thanks to its low cost and high bandwidth. The current proposals to achieve real-time communication over Ethernet do not consider the determinism of the control applications resulting in inefficient use of bandwidth resources. We proposed a protocol stack architecture that works with standard Ethernet to address this problem. This paper describes...
A clock skew-compensation and/or duty-cycle correction circuit (CSADC) is indispensably required to maximize the performance of synchronous double edge triggered systems. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more power consumption and design complexity. A range...
A high-speed dual-phase domino circuit design with high performance and reliable characteristics is proposed. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64-bit high-speed multiplier with a built-in performance adjustment mechanism has been successfully validated using TSMC 0.18um CMOS technology. The test chip shows a...
Orthogonal Frequency Division Multiplexing (OFDM) is considered as an effective method for overcoming problems such as noise, multi-path propagation and frequency selective fading in low voltage power-line communication (PLC). However, OFDM system is sensitive to the error of synchronization. Accurate symbol timing and carrier frequency offset estimation are crucial to the PLC system based on OFDM...
Delay mismatch between the input and output signals of power amplifiers (PAs) may lead to an erroneous assumption of memory effects. In adaptive digital predistortion (DPD) system, the delay mismatch affects the accuracy of coefficients estimation and degrades performance of the DPD system. In this paper, we reveal the impact of fractional delay mismatch, and analyze the relationship between delay...
Localization and synchronization are critical challenges for a wireless network, which are conventionally solved independently. Recently, various estimators have been proposed to jointly synchronize and localize a node in a static network based on two way communication. In this paper, we present a novel and generic model based on two way communication between nodes, which are in relative motion with...
This paper presents a method for time base synchronization between independent nodes which communicate over a wireless medium. It is shown that the malicious effects of multipath propagation are minimized and precise time base synchronization is achieved.
This paper presents a method for time base synchronization between independent nodes which communicate over a wireless medium. It is shown that the malicious effects of multipath propagation are minimized and precise time base synchronization is achieved.
Exploiting the increasing ubiquitous deployment of sensor networks, the paper presents a system called WiBee that utilizes ZigBee sensors to build real-time WiFi radio maps. The design of WiBee is motivated by the observation that a ZigBee radio can sense WiFi frame transmissions although it cannot decode WiFi frames. A sensor passively listens on the wireless channel and estimates the RSS of a WiFi...
Energy-constrained wireless sensor networks are duty-cycled, relaying on multi-hop forwarding to collect data packets. A forwarding scheme generally involves three design elements: media access, link estimation, and routing strategy. Most existing studies, however, focus only on a subset of those three. Disregarding the low duty cycle nature of media access often leads to overestimate of link quality...
Along with the growth of cloud computing and mobile devices, the importance of client device identity concern over cloud environment is emerging. To provide a lightweight yet reliable method for device identification, an application layer approach based on clock skew fingerprint is proposed. The developed experimental platform adapts AJAX technology to collect the timestamps of client devices in the...
Synchronization of large-scale networks is an important and fundamental computing primitive in parallel and distributed systems. The synchronization in cellular automata has been known as firing squad synchronization problem (FSSP) since its development. The FSSP has been studied extensively for more than fifty years, and a rich variety of synchronization algorithms have been proposed so far. In the...
The wormhole attack is a severe attack in Wireless Mesh Networks (WMNs). It involves two or more wormhole endpoints colluding to capture traffic from one place in the network and replay it to another faraway place through a secret tunnel, so as to distort network routing. It may lead to even more serious threats such as packet dropping and denial of service (DoS). Although a lot of works have been...
Contemporary digital systems must be based on the “System-on-Chip — SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays), but the implementation of asynchronous interfaces (asynchronous wrapper — AW) constitutes a major drawback for this kind of devices...
We designed a scalable distributed wireless network emulator for high-speed mobility. Wireless network emulators provide various conditions of mobile nodes' dynamics and wireless links to real implementation of protocols to be evaluated based on user-defined mobility scenarios. The target of the proposed emulator is IP-based protocols for large-scale mobile wireless networks composed of a large number...
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