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Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and do not generate coherence traffic, but they...
Self-checking algorithms are used to ensure a software executes as intended. This guarantee is important not only to protect software against piracy, but also in order to avoid third parties to illegally modify it and introduce malicious code with the purpose of infecting users. In this paper, we present the implementation aspects of a self-checking algorithm for Adobe Flash Applications.
End applications like automotive, mobile, industrial, communications and infrastructure require hardware architectures with multiple processing elements to reduce overall system cost and power. Typical hardware architectures consist of multiple processors to meet computational needs along with a rich set of peripherals to meet connectivity requirements. The complex interaction between the processing...
In the open hardware graphics accelerator (ORGFX), there are rectangle, line, triangle and curve rasterization modules. This paper is only focused on the improvement of line rasterization speed. Besides modifying the algorithm itself, hardware implementation and resource consumption are put into consideration here. Originally, ORGFX uses the classic Bresenham line algorithm with high precision and...
Data-parallel architectures must provide efficient support for complex control-flow constructs to support sophisticated applications coded in modern single-program multiple-data languages. As these architectures have wide data paths that process a single instruction across parallel threads, a mechanism is needed to track and sequence threads as they traverse potentially divergent control paths through...
This paper investigate the analysis of power and area of Advanced Encryption Standard (AES) algorithm using different design tool like ARM based, Hardware (VHDL/Verilog) and HW/SW. Results of area and power consumption for different design are varying and the percentage improvement in the power and area is marginable.The power improvement range is between 22.5% to 90% and the area improvement range...
A complete framework and methodology to design, simulate, and debug large SoC is presented. Full VP creation using efficient tools is described. An efficient tool to allow co-debug of HW/SW on VP is also presented. The tools enable debugging and analyzing an application and a Linux driver that run on the VP. Breakpoints and mon commands can be used to detect and correct errors, access registers and...
Keccak is the hash function selected by NIST as the new SHA-3 standard. Keccak is built on Sponge construction and it provides a new MAC function called MAC-Keccak. These new algorithms have raised questions with regards to side-channel leakage and analysis attacks of MAC-Keccak. So far there exists prior work on attacks of software implementations of MAC-Keccak, but there has been no comprehensive...
Feature selection in pattern recognition is a problem whose space complexity grows exponentially regarding the number of attributes in a dataset. There are several hardware implementations of algorithms for overcoming this complexity. These hardware architectures relay on a software component for filtering irreducible features subsets, which is a computationally complex task. In this paper, a new...
The In-circuit-Tester (ICI) demands large volume of physical test points on PCB, which makes the PCB size bigger and also the cost of ICT test technology is very high, so there is a need for low cost PCB test technology, which allows the miniaturization of PCBs with simple design rules[1]. The solution is ‘Boundary Scan’. Implementation of IEEE1149.1boundary scan test standard into the ICs contributed...
Software exception analysis can not only improve software stability before putting into commercial, but also could optimize the priority of patch updates subsequently. We propose a more practical software exception analysis approach based on taint analysis, from the view that whether an exception of the software can be exploited by an attacker. It first identifies the type of exceptions, then do taint...
The significant disadvantage of Android Operating System is Dalvik bytecode interpretation using Dalvik Virtual Machine (VM) [1], [2]. However there are many techniques [3] to improve the performance of VM. In this paper, we propose an alternative methodology which is "Fetch/Decode Hardware Extension with hybrid Execution". It is a particular hardware that specially designed to fetch and...
Camellia, a block cipher jointly developed by Mitsubishi and NTT of Japan, is suitable for both software and hardware implementations and more secure than AES cipher. One of design-for-test techniques using scan chains is called scan-path test, in which testers can observe and control registers inside the LSI chip directly. Recently, scan-based side-channel attack is reported which retrieves the secret...
Detecting vulnerabilities in binary codes is one of the most difficult problems due to the lack of type information and symbols. We propose a novel tool to perform symbolic execution inside the routines of binary codes, providing easy static analysis for vulnerability detection. Compared with existing systems, our tool has four properties: first, it could work on binary codes without source codes,...
The MEMOCODE design contest for 2014 was centered around the emulation of the 1978 Taito video game Space Invaders. The challenge is to improve the speed of a cycle-accurate software emulator for the game. Contestants had a month toope improve the provided code, which already ran fairly well on the ARM-based Raspberry Pi platform. Entries were judged on how much faster their code ran and its quality...
LED test can be done in several stages of the manufacturing process of a device. Although ICTs can check the electrical parameters of LEDs, they do not always have extensions for chrominance and luminance measurements. This paper presents a test system for both colour and light intensity of LEDs, designed to communicate with a computer via USB. Test system has a graphical interface that allows operation...
This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. This study evaluates the strengths and weaknesses of this new architecture exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench [1] and the CLOMP-TM [2] benchmarks....
Return-oriented programming is a kind of codereuse technique for attackers, which is very effective to bypass the DEP defense. However, the instruction snippet (we call it gadget) is often unprintable 1. This shortcoming can limit the ROP attack to be deployed to practice, since non-ASCII scanning can detect such ROP payload. In this paper, we present a novel method that only uses the printable gadgets,...
Complex Event Processing (CEP) is an emerging field in high performance computing paradigm where real time (low latency) computing capability is expected over big data processing (high throughput). Significant number of software architectures have been developed to improve the throughput while reduce the latency but maintaining of the both aspects reaches the limits of the software platforms. This...
In order to dynamicly monitor and manage the working state of space science experiment payloads, the large volume of science data should be performed for real-time transmission. According to this requirement, the paper proposes a design scheme of main information network based on Ethernet. A microprocessor TMS320F2812 and the Ethernet interface chip KSZ8851 are applied to set up the Ethernet communication...
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