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Digital Front End Reconfiguration is considered one of the most promising techniques to implement the Software Defined Radio (SDR) and the Cognitive Radio (CR), allowing the same set of hardware to accommodate Multi-Standard Communication Systems (MSCS). The benefit increases when the reconfiguration is not only dynamic but also takes place in real time without the need to switch off the system. This...
When considering Elliptic Curve Cryptography (ECC) implementations, countermeasures against side channel attacks are primarily focused on elliptic curve arithmetic. On the other hand, Elliptic Curve Digital Signature Algorithm (ECDSA) implementation also uses a modular multiplication of a private key dA, and publicly known random parameter r. The side channel leakage of the multiplication rdA can...
Dynamic Circuit Specialization (DCS) is a technique for optimized FPGA implementation and is built on top of Partial Reconfiguration (PR). Dynamic Partial Reconfiguration (DPR) provides an opportunity to share the silicon area between different Partially Reconfigurable Modules (PRMs) and therefore results in smaller and faster designs that potentially also reduce the power consumption. In this paper,...
Internet of things and cyber-physical systems requiring security functionality has pushed for the design of a number of block ciphers and hash functions specifically developed for being implemented in resource constrained devices. Initially the optimization was mainly on area and power consumption, but, nowadays the attention is more on the energy consumption. In this paper, for the first time, we...
Hardware acceleration is often used to address the need for speed and computing power in embedded systems. FPGAs always represented a good solution for HW acceleration and, recently, new SoC platforms extended the flexibility of the FPGAs by combining on a single chip both high-performance CPUs and FPGA fabric. The aim of this work is the implementation of hardware accelerators for these new SoCs...
Increasing computation demands with limited power budget require more energy-efficient designs without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing is an alternative to optimize both performance and power consumption. However, due to the complexity of hardware design, implementing dedicated accelerators usually lacks flexibility and productivity...
In this work, we designed a Visitor Counting Machine (VCM) in terms of power efficient circuit using family of three different IO Standards which are LVTTL, Mobile DDR, HSUL 12. These three different IO Standards are compared with each other on the basis of Clock power, Logic power, Signal power, IOs, Leakage power and Total power consumption to search the most power efficient one. In order to find...
This paper elucidates the replicating of a human brain which is energy efficient. The power consumption factor has been highly focused in this research. Attempts have been made to study those conditions at which the consumption of power is minimum. An artificial human brain is advantageous over the real brain due to the fact that it has a higher accuracy, it can perform those rigorous calculation...
This paper contains designing of energy efficient memory circuit using two different IO standard i.e. LVTTL and Mobile-DDR on 28nm (Artix-7) Field Programmable Gate Array. We are using Xilinx ISE simulator version 14.2, Verilog hardware description language and Artix-7 FPGA. The design has been tested at different operating frequencies of Latest Intel processor that are at Intel I-3, Intel I-5 and...
Now-a-days, energy considerations are major concern of every circuit design, every designer tries to minimize the energy utilization by using different techniques. In this research we have considered number of smart wireless sensor nodes and varied the supply voltage and observed the change in power dissipation due to clock frequency and total power dissipation at different frequency ranges of wireless...
To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application...
Designing a high performance and energy efficient image processing solution for a very limited platform of a small UAV (Unmanned Air Vehicle) is very challenging. We address this issue by conducting a research of low power (under 10 Watt) and small sized (slightly larger than a credit card) embedded platforms with high performance computing capabilities. Sobel filter algorithm used in image processing...
Coarse-Grained Reconfigurable Architecture (CGRA) is a promising accelerator when considering both high performance and high power-efficiency. One of the challenges that CGRAs are confronting is to accelerate loops with control flow (if-then-else structures). Existing techniques employ predication to accelerate the conditionals but cannot accelerate nested conditionals efficiently. The state-of-the-art...
In surveillance and scene awareness applications using power-constrained or battery-powered equipment, performance characteristics of processing hardware must be considered. We describe a novel framework for moving processing platform selection from a single design-time choice to a continuous run-time one, greatly increasing flexibility and responsiveness. Using Histogram of Oriented Gradients (HOG)...
We are all longing for high speed, flexible, robust and low power processing system in the world. FPGA architecture is gathering attention due to one order less magnitude of power saving as one of non-Neumann approach. Other approach is like unified block included small logic, small memory and small controller which is announced by eASIC, nextrame-2/3(1) or Synopsis, EVP(2) as examples which are instead...
Accurate characterization of real device samples is essential for understanding the true potential of the emerging non-volatile memories (NVMs) and identifying their optimal placement in the memory hierarchy. Even though, NVM devices are now available from different manufacturers, lack of an appropriate NVM controller and evaluation platform in the public domain is the main challenge in extracting...
A circuit technique based on hardware replication improves the robustness of the FPGA circuitry against dynamic and/or static power attacks. Due to its nMOS-MUX based structure, the proposed circuit also exhibits an increased robustness against early evaluation attacks and those based on glitches. The secured LUT and switch are 3.4× and 1.5× larger than their standard counterparts, respectively. Given...
Error detection and correction (EDAC) functions have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturing technologies. This paper presents three novel synthesis algorithms that obtain area-efficient implementations for a given EDAC function, with the ultimate aim of reducing the number...
The seeker signal processor is a key device of a seeker. Based on the common characteristics extracted from seekers with different architectures, a general-purpose hardware scheme based on Field-Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) is proposed. By taking full advantage of the FPGA and the DSP, the signal processor is equipped with the ability of high speed and real-time...
Mobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for...
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