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The Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Our kiwic compiler takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. In this brief paper, we describe attributes used to mark up I/O nets, embed assertions,...
Traditional design techniques for FPGAs are based on using hardware description languages, with functional and post-place-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a...
This paper presents a digital cellular neural network (CNN) for digital image processing applications. The CNN is a relatively new field in this research, making use of a high degree of parallelism to achieve higher levels of processing power which continuously paves new ways of how problems can be tackled. A digital architecture is employed due to the fact that digital devices allow for a very robust,...
This paper deals with the automatic translation of interpreted generalized Petri Nets with time into VHDL, for rapid prototyping on programmable logic device purposes. This approach is based on the component orientation of the VHDL language, and defines two elementary VHDL components: the place and the transition. This transition component is a "pivot" element of the approach, since it supports...
The objective of this paper is to determine the effects of 'loop-unrolling' design concept, on the performance of hardware based implementations of the RC5 encryption algorithm. An effort has been done to determine the best value of the number of unrolled loops to implement the RC5 algorithm using 192-bit encryption key. The various models tested were based on single-custom processor with: no-loop-unrolling;...
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we extend and adapt an existing outer loop pipelining approach known as single dimension software pipelining to generate schedules for field-programmable gate-array (FPGA) hardware coprocessors. Each loop level in nine test loops...
In this paper we present a trade-off analysis between hardware size and speed performance, measured in clock cycles, concerning fixed-point, memory-based FFT processors designed for FPGA. For OFDM systems using fixed-point FFT processors we also provide bit width requirements for different FFT sizes and digital modulation schemes including QPSK, 16-QAM, 64-QAM, 256-QAM. The information provided is...
This tutorial addresses the challenges and opportunities presented by compiled FPGA-based code accelerators. In recent years we have witnessed a fast growth of both size and speed of FPGAs. These had been initially designed and marketed as convenient devices for “glue logic.” Later, they became used as fast prototyping platforms. As their size and speed grew, they have been used for the short time...
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