The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Power dissipation is a bottleneck in the design of low power electronic devices that, operate at high frequencies. Hence, the clock signal is a major source of power dissipation. The technique clock gating at the architecture level can be implemented to reduce the dynamic and clock power. In this paper, the authors aim at implementing, analyzing and comparing the various resource power using clock...
We propose an Asynchronous-to-Synchronous Interface Controller (A2S-IC) with low delay-variation towards Process, Voltage and Temperature (PVT) variations for sub-threshold/near-threshold operation in low power applications. This A2S-IC is targeted for a full-range Dynamic Voltage Scaling (DVS) Global-Asynchronous-Local-Synchronous (GALS) Network-on-Chip (NoC). There are three key attributes in this...
The integration of a variety of IP cores into a single chip to meet the high demand of new applications leads to many challenges in timing issues, especially the interface between different clock domains. Globally Asynchronous, Locally Synchronous (GALS) approach addresses these challenges by dividing a chip into several independent subsystems working with different clock signals. In multi-synchronous...
The Smart Home is based on the Wireless Sensor Network (WSN) and Embedded System (ES). The most important parts of the Smart Home are low-power and high-security. And it is very vulnerable to various attacks ether an active or passive one in WSN. We shed light upon some existing security flaws in W2 and ZigBee. Some are quite useful to defend the various attacks, but don't suit for the Smart Home...
Pausible clocking is a very popular approach for clock domain interfacing in GALS systems. However, accuracy and stability of the ring oscillator that is central to this principle are bad. This suggests to use gated crystal oscillators instead. In this paper we will formally show that the problem of clock gating is equivalent to the synchronization problem. We will present a fundamental block diagram...
In this paper the prototype of an IEEE 802.15.4 compliant multi-hop wireless sensor network for energy-efficient sensor data and progressive image data transmission is proposed. For progressive transmission of JPEG and JPEG2000 encoded images a proprietary code stream has been developed. The JPEG and JPEG2000 codecs have been implemented in software. For the implementation of the wireless sensor network...
The novel design of a 8-bit decision module that forms the heart of a dynamic CMOS incrementer-cum-decrementer circuit is presented in this work. The new 8-bit decision module is designed on the basis of identifying least significant zero bit (LSZB) in the binary input stream contrary to identification of least significant one bit (LSOB), as is the case with existing approaches, to perform increment-cum-decrement...
The design of a pipelined SCL 8051 ALU is elaborated. Two versions of SCL gates are considered for gate-level implementation: SCL gates with both nsleep and sleep signals and SCL gates without nsleep signal. In both versions all combinational blocks, registers, and completion components can be put to sleep mode. In addition, the problem associated with pipelining the SCL 8051 ALU is explained and...
Wireless Sensor Networks (WSNs) are rapidly becoming a necessary tool in many different application areas, such as environmental monitoring, security, safety, and so on. The heterogeneity of hardware is large, so there exists several different environments that support WSN programming. However, the great majority of such environments only target the sensors programming, forgetting about their real...
A system implementation framework is presented for configurable high-speed IP over AOS gateway in this paper. Pipeline operation and asynchronous FIFOs are adopted to achieve rate matching and data synchronization between different clock domains. The format of configuration packet of IP over AOS gateway and finite state machine description of protocol are given. The simulation results show that the...
Several solutions for implementing Petri net models on FPGA thanks to a transformation in a VHDL code have been proposed in literature. But none deals with the management of transition conflicts in the specific case of synchronous implementation of interpreted Petri nets. This article presents an automatic method to deal with conflicts from their detection to their implementation on FPGA. One solution...
This paper describes a fully-integrated 77-GHz distant-selective pseudo-random noise coded Doppler radar transceiver in a Silicon-Germanium technology. The transceiver is capable of measuring a vibration or a velocity of a target at a specified distance, which is programmable and can be configured very precisely in the transceiver, and suppressing all other targets elsewhere. It is equipped with two...
This paper describes a SAR ADC interface circuit, where the input sensing voltage from a bipolar high voltage domain is linearly translated into the low voltage domain where the SAR ADC operates. The proposed interface circuit employs the principle of charge transfer amplifier to deliver information between two different power domains, in one step, without static power consumption, even if both domains...
Asynchronous design is predicted to have a significant place in the future due to benefits of speed, power consumption, and design. Null Convention Logic (NCL) is a subcategory of asynchronous design that results in the most reliable and low-power asynchronous hardware. However, test strategies are not adopted to match the characteristics of this important asynchronous method, and the existing test...
The business process model is commonly created as a fundamental high level analysis model. The BPMN is one of the well known and widely used to represent the business process model. Recently, the BPMN workflow patterns are proposed as standardized business process model building blocks. The BPMN workflow patterns also provide the business analysts the common patterns of solutions to various workflow...
Power management is an important part of modern microelectronics, however, the possibilities for its design automation are insufficiently studied and therefore the state-of-the-art synthesis methods produce suboptimal power control circuits. Currently the same design principles, which are based on synthesis of synchronous state machines, are used for both the data processing components and the power...
The phased clock signals are useful to synchronize the individual modules within a multiphase digital system and satisfy the complexity of their clock timing requirement. The capability of the on-demand adjustment of the phased clocking pattern can be embedded to the circuit that generates the associated clocks by shifting in time their active clock edges. A delay insertion technique is presented...
Control and data dependencies represent prominent information for modeling, managing, testing and optimizing service based business processes (SBPs). BPMN 2.0, as a twofold-purpose language, can be used to both mode land execute these SBPs. However, there is neither tailored support nor implemented tool for dependency ananlysis of such processes. Therefore, in this paper, we designed and implemented...
Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, programmable logic devices such as FP-GAs are the implementation platform of choice due to their higher flexibility compared to ASICs and lower power...
The software architecture community has proposed to document the design rationale of software architectures by means of architectural design decisions (ADDs). The constant evolution of software systems requires that both architectural designs and corresponding ADDs are continuously documented and synchronized. However, in practice, designs and ADDs become inconsistent over time. Usually, the potential...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.