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A 5 V, 0.6 mum CMOS phase locked loop (PLL) is presented. The circuit design of the PLL, which consists of a phase-frequency-detector (PFD), charge-pump (CPP), bias-generator (BG), voltage controlled oscillator (VCO) and differential to single converter (DSC), is introduced and the simulation results are given. The details of design theory and calculation are also described. The PLL is integrated...
A complete CMOS wideband low noise amplifier (LNA) has been designed with off-chip passive device. The input inductor with integrated passive device (IPD) is used for input matching and NF improvement due to its high quality factor (Q). The large inductance of 4.7 nH of choke is used for covering the bandwidth of 2~11 GHz, which is stacked on the top of CMOS for chip-area saving. Besides, the interaction...
A single-stage stacked-FET power amplifier (PA) is demonstrated using a 0.28-mum silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. The stacked-FET PA has been designed to withstand up to 9 V of supply voltage before...
A CMOS fully differential UHF variable gain amplifier for use in a direct-conversion DVB-H receiver is presented employing input devices with variable aspect ratios. High linearity is achieved by reducing the transconductance of the input transistors for lower gain settings. It is shown that this technique has better linearity and noise performance compared to the conventional methods in which the...
A receiver front-end in standard 45 nm CMOS technology is presented. The receiver achieves WCDMA system performance without requirement for an inter-stage SAW filter. High out-of-band linearity performance is achieved by reducing the RF circuitry and filtering the out-of-band blockers after direct conversion. For the receiver at 1.9 GHz, a +3.1 dBm IIP3 is achieved for blockers at 40 MHz and 80 MHz...
A quadrature voltage-controlled oscillator (QVCO) based on the time-varying gate-modulated coupling of two LC tank VCOs is introduced. Using a standard 0.18 mum CMOS process, the new topology is compared to the conventional series QVCO in terms of start-up loop gain, quadrature phase accuracy, phase noise, tuning range, and voltage headroom characteristics. In addition to comparable phase noise performance,...
We fabricated a multiband transceiver for mobile WiMAX in 90-nm CMOS technology. It operates at three RF bands (2.3/2.5/3.5 GHz) with a large dynamic range. We adopted a double conversion receiver that can switch lower and upper local modes. An image rejection ratio (IRR) tunable single side-band (SSB) mixer was used to achieve over 50 dB IRR. The RCE for 2.5 GHz at -71.5 dBm input was -28.7 dB and...
A fully integrated transmit chain for 802.11a band with on-chip power amplifier and on-chip balun matching network in 45 nm standard digital CMOS process demonstrates saturated power of +23 dBm. The average efficiency is +5% and peak efficiency is +15%. A standalone class AB CMOS power amplifier with on-chip balun matching network was also produced and detailed characterization data is presented....
The highly efficient CMOS power amplifier module (PAM) is designed for quad-band cellular handsets comprising GSM850, EGSM, DCS, PCS and supports Class 12 general packet radio service (GPRS) multi-slot operation. This module integrates an input matching network, a complete power control, and a thermal, over current, and load mismatch protection in a standard RF CMOS process and also contains a high-Q...
This paper describes an ultra-low-power RF transceiver implemented as part of a system-on-chip. The transceiver operates in the 868/915 MHz frequency band using binary FSK modulation at a 45 kbit/s data rate. It achieves -89 dBm receiver sensitivity and -6 dBm transmitter output power while consuming 1.6 mA and 1.8 mA, respectively, from a 1.2 to 1.5 V supply. It is fabricated in 0.13 mum CMOS occupying...
A novel resonant circuit consisting of transformer-based variable inductors and MOS varactors is proposed to implement an ultra-wideband voltage-controlled-oscillator (VCO). The VCO is designed and fabricated using 0.13 mum CMOS, and fully evaluated on wafer. The VCO IC exhibits a frequency tuning range as high as 92.6 % spanning from 1.2 GHz to 3.27 GHz. The measured phase noise of -120 dBc/Hz at...
This paper presents a feasibility study of a low power electronic RF tagging device and a printed capsule antenna for medication compliance monitoring. RF transponders attached directly to the outer surface of a standard sized capsule can potentially serve as a cost-effective method of validating medication compliance via electronic detection of an ingested pill inside the digestive tract. The electrical...
This paper presents the design and implementation of a low-voltage down-conversion mixer in 65 nm CMOS technology for UWB applications. The folded circuit topology with AC-coupled inverter based RF transconductance stage operates under low voltage conditions of 1.2 V with a peak gain of 14.5 dB and a 3-dB-bandwidth from 1 GHz to 10.5 GHz with 1 dBm LO power. The input referred compression point is...
A VCO is fabricated in 0.35 mum CMOS technology for tuner application as a proof of concept for a novel method of resistively tuning the inductance of an LC VCO. By employing a transformer as inductor, L is varied by changing the secondary coil current using active resistors. This eliminates the need for using multiple inductors to cover the frequency spectrum of 1.1 to 1.9 GHz, resulting in large...
This paper reports a flexible direct digital modulation based low power transmitter in 90 nm CMOS that supports constant-envelope modulation using phase or frequency modulation for carrier frequencies from 100 MHz to 2.5 GHz. For rectangular filtered 8-PSK modulation from 1 K symbol/s to 20 M symbol/s the RMS phase error is less than 4 deg. Frequency modulation is measured via filtered frequency shift...
A study based on improving linearity of an integrated RF power amplifier (PA) has been done for W-CDMA standard. This power amplifier had been designed in 65 nm CMOS of STMicroelectronics under Cadence. The chosen linearization technique is a Cartesian Feedback (CFB). Thanks to this linearization technique, the ACPR has been improved by 22 dB at 5 MHz from the carrier for an output power of 18 dBm.
A Manchester code generator designed at transistor level with NMOS switches is presented. This generator uses 26 transistors and has the same complexity as a standard D flip-flop. It is intended to be used in a complex optical communication system. The main benefit of this design is the use of a clock signal running at the same frequency as the data. Output changes on the rising edge and falling edge...
This paper presents a dual-band low power voltage-controlled oscillator (VCO) with only one single control signal. This VCO is designed in TSMC 0.18 um CMOS process to cover the frequency bands of 2.45~2.85 GHz and 3.41~3.7 GHz for WiMAX applications. With 1.5 V supply voltage, the simulated power consumption of the core VCO is 3.17 mW. The simulated phase noises at 1-MHz offset frequency are -122...
This paper presents a continuous frequency tuned bulk acoustic wave (BAW) resonator based oscillator without varactors. The frequency of oscillation is derived by interpolating between the resonant frequencies of two different resonators. Changing the interpolation factors allows a continuous tuning of the oscillation frequency between these two resonant frequencies. A proof of concept circuit was...
An arbitrary-input pulsewidth control loop (AIPWCL) based on a delay-locked loop with duty cycle corrector is presented. The duty cycles of the clock signals can be adjusted from 10% to 90% in 10% steps. The proposed AIPWCL is designed and simulated by using tsmc 0.13 mum CMOS process. The operation frequency range is from 770 MHz to 1.05 GHz. The locking time of AIPWCL is less than 40 ns within the...
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