A 5 V, 0.6 mum CMOS phase locked loop (PLL) is presented. The circuit design of the PLL, which consists of a phase-frequency-detector (PFD), charge-pump (CPP), bias-generator (BG), voltage controlled oscillator (VCO) and differential to single converter (DSC), is introduced and the simulation results are given. The details of design theory and calculation are also described. The PLL is integrated in CMSC 0.6 mum 5 V 2P2M CMOS technology, the simulation results show that the PLL operates within the frequency range between 100 MHz to 500 MHz, and the phase noise are -89 dBc/Hz and -100 dBc/Hz at 100 KHz and 1 MHz offset frequency.