The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 900 MHz direct-conversion receiver for UHF RFID readers with low power, high linearity, and low noise in UMC 0.18 ??m CMOS technology is proposed. This receiver possesses I/Q two paths and each path consists of a passive mixer, an IF amplifier, a RC low-pass filter and a comparator. It supports a LO frequency from 860 MHz to 960 MHz and a data rate from 40 kb/s to 1 Mb/s which are in accordance...
This paper presents a low-power down-conversion mixer for 3.1~4.8 GHz MB-OFDM UWB applications. The proposed mixer is based on folded double-balanced Gilbert cell and employs following techniques: two cross-coupling capacitors at the transconductance stage enhance conversion gain and reduce input noise; two choke inductors reduce flicker noise from the switch quad; tuning capacitors and resistors...
A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue pre-charging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that the ADC obtains a SNDR of 23.7 dB at Nyquist input frequency and consumes 430 ??W from a 1 V supply...
This article presents a 60 GHz low-power injection-locked oscillator in TSMC 65 nm technology. By using the frequency sweeping technique, a simulated 7 GHz total locking range is achieved, which covers the entire 60 GHz ISM band. The simulated settling time is less than 2 ns for each sweeping step with -60 dBm injection power. The DC power consumption is 1 mW of the oscillator core, and 5 mW in total...
Comparator is the key module in LDPC decoder that consumes most of the power and area. In this paper, a new comparator based on pass transistors and dynamic logic is proposed to decrease the power and the area. The comparator is implemented with full custom design at SMIC 0.18 1P6M technology. The simulation result of layout shows that the power drops by 11.4% and the area is reduced by 30% compared...
This paper describes a high-dynamic-range 2.4 Hz-to-10 kHz wide-range tunable 5th-order Butterworth lowpass filter for biomedical applications. A differential gm-C topology in conjunction with a subthreshold-biased wide-gm-range OTA realizes efficiently a wide frequency tuning capability. For capacitance savings with consequent silicon area reduction, a merged use of floating real capacitor and grounded...
A level converter circuit for I/O ports from 3.3 V LVTTL logic to 1.8 V CMOS logic with TSMC 0.18 um CMOS process has been designed. Level converter circuit has been integrated in an integrated circuit, which use single supply voltage. A positive feedback circuit similar to the Schmitt flip-flop is adopted to realize the level conversion, which also acts as both a buffer and a waveform shaping role...
The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increases, resulting in a much higher...
A switch-capacitor SDM with a controllable gain design at the signal input stage has been proposed. This gain control is realized by increasing the input sampling capacitors to obtain a higher signal gain of the first integrator. This method can greatly reduce the switch-capacitor thermal noise due to the input sampling capacitors without degrading the SDM noise shaping feature. The adaptive gain...
A modified regulated cascode structure having high output swing capability is presented. This structure is used in the implementation of a current mirror. The current mirror possesses wide input and wide output swing capabilities, suitable for low voltage operation. P-SPICE simulations at 0.25 ??m CMOS technology validate the proposed current mirror for currents from 30 nA to 220 ??A, at 1 V with...
This implementation of sequential logic circuits by using a novel quasi-static single-phase adiabatic dynamic logic (SPADL) has been presented. SPADL uses only a single sinusoidal source as supply-clock. This not only ensures lower energy dissipation, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Simplicity and static...
In nanoscale analog CMOS design there is no good substitute for understanding reliability stress factors or the many effects related to the circuit physical layout which can cause significant design-for-reliability (DFR), performance (DFP), or manufacturability (DFM) yield degradation. Circuit simulation tools presently lack the capability to predict the effect of several stress and reliability effects,...
A multirate 3rd order modulator targeting GSM standard is presented in this paper. Dynamic Element Matching technique to improve the linearity for the 4-bit DAC in the external feedback path is described. High-level simulations give a maximum SNDR of 79.98 dB while simulation results for a prototype made in a standard 0.6 ??m CMOS technology show that the SNDR at the transistor level achieves 78.47...
As the temperature increases, interconnect delay increases due to the linear increase in electrical resistivity. This degrades the performance and shortens the interconnects life time. Package reliability will also be severely affected by the resulting thermal hotspots, thus impacting the overall performance of multicore systems. We approach this challenge by proposing to use thermal management techniques...
An ultra-low-power LC quadrature VCO (QVCO) is presented. It is designed in a single-poly seven-metal 65 nm CMOS process. To minimize power dissipation an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (fo) of 3.8 GHz, was designed. According to SpectreRF simulations the power dissipation is below 250 ??W at a 0.6V supply. At this supply the simulated tuning range...
In this paper, we present a low voltage, low power, 2.4-GHz frequency synthesizer designed in 0.35-μm CMOS technology. The frequency synthesizer is implemented with an Integer-N phase-locked loop (PLL). The PLL can achieve a frequency tuning step of 1-MHz and is capable of covering the whole 2.4-GHz ISM band. The voltage controlled oscillator (VCO) output frequency is firstly divided by a novel tri-modulus...
In this paper, we present a new wideband low noise amplifier which operate in UHF band for spectral sensing in the receiver of cognitive radios. The circuit employs the noise-canceling technique, and can achieve the higher gain and lower power dissipation. The method of shunt-resistive feedback is adopted for achieving a broad bandwidth. The LNA is designed by the CMOS 0.18 um RF technology. Simulated...
This paper proposes the design and analysis of a broadband 2-40 GHz passive distributed drain-pumped mixer using 0.18 μm CMOS technology for ultrawide-band (UWB) receivers. To achieve broad bandwidth for the UWB communications, a distributed topology is introduced. A closed-form analytical model for the conversion loss of distributed drain-pumped mixer is presented for the first time. The designed...
A 1.1 mW 87 dB dynamic range 3rd order ΔΣ modulator is implemented in 0.18 μm CMOS technology for the audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed and only one simple current mirror single-stage OTA with 34 dB DC gain is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB...
A dual core wideband voltage-controlled oscillator (VCO) with small VCO tuning gain fluctuation ( KVCO variation ) is presented. This integrated VCO has a wide tuning range from 1.8 GHz to 3.8 GHz, which can provide all desired frequency band for China Mobile Multimedia Broadcasting (CMMB) receiver. A 5-bit switched capacitor bank and a self-controlled varactor pair is used in each core to achieve...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.