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Pre-bond testing of 3D ICs improves yield by preventing bad dies and/or wafers from being used in the final 3D stack. However, pre-bond testing is challenging because it requires special scan chains and power delivery mechanism. Any 3D scan chains that traverse multiple dies will be fragmentized in each individual die during pre-bond testing. In this paper we study the scan chain and power delivery...
In this paper, we review a recently developed transformative nanowire FET sensor concept and 3D-compatible fabrication technology. Compared to the generic nanowire FET sensors, an intrinsic boost in detection sensitivity is accomplished through the seamless integration of a sensing nanowire with an amplifying nanowire FET. Exclusively enabled by top-down nanofabrication technology, the back-end-of-line...
System-level interconnect structures become much more complicated and dominate overall performance in multi-core systems. In order to facilitate interconnect test in board-level and system-on-chip (SoC) designs, IEEE standards 1149.1 and 1500 are developed. Dedicated design-for-testability (DFT) architectures for interconnect consisting of through-silicon via (TSV) in future 3-D stacked ICs have also...
Three-dimensional Stacked Integrated Circuit packages interconnected using high speed Through-Silicon Via technology can be efficiently manufactured using a wafer-to-wafer stacking process. Efforts to mitigate degradation in the composite yield of the stacked die are primarily focused on matching defect maps while assigning the pre-tested wafers from the available wafer repository to individual wafer...
Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test...
In this paper, the new elements in 3DIC are examined for enabling optimal 3D products: including 3D interconnect which maybe the limiting factor to achievable speed; 3D chip design strategy (partition and implementation) to achive optimal performance; wireless testing to address the challenges in testing a partial system / chip before stacking and with limited observation points after stacking.
Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low temperature direct bonding and wafer thinning (figure 1). This technology is adapted for advanced semiconductor applications such as Back Side Illumination...
Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking), or MEMS structure packaging. Different alternatives are currently investigated such as via-first or via-last. Into the via-first family two different...
Asynchronous communications are foreseen as mandatory for implementing 3D multiple tiers circuits. The drawback of asynchronous rails compared to synchronous ones is the higher number of interconnects. This number needs to be decreased when horizontal interconnects are replaced by Through Silicon Vias (TSV) because of their big silicon footprint. A circuit using only one TSV for asynchronous, quasi...
3D integration is a promising new technology that offers numerous potential benefits including reduced wire length, high tier-to-tier bandwidth and low latency, and the possibility for heterogeneous integration of disparate technologies. As a result, 3D integrated circuits (IC) are being aggressively investigated as a potential replacement for conventional planar ICs in both academia and industry.
The following topics are dealt with: model order reduction; signal and power integrity analysis; 3D IC interconnects; nano-interconnects; degradation and parasitic effects; macromodeling; and transmission lines and waveguides.
The optimization of grinding parameters for silicon wafers is necessary in order to maximize the reliability of electronic packages. This paper describes the work performed to simulate a back grinding process for Through Silicon Via (TSV) wafers using the commercial finite element code ABAQUS. The grinding of a TSV silicon wafer with a thickness of 120 μm mounted on a backing tape was simulated. The...
The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu,...
As a consequence of increasing functional density and miniaturization in microelectronics new low-k and ultra-low-k materials are going to be increasingly used in Back-end of line (BEoL) layers of advanced CMOS technologies. These ongoing trends together with the transition to the use of TSVs for 3D-IC-integration cause novel challenges for reliability analysis and prediction of relevant electronics...
Large and complex system-on-chip devices consisting of many processor cores, accelerators, DSP functions and many other processing and memory elements are becoming common in the semiconductor industry nowadays. To communicate, these processing and memory elements need to have a network-on-chip (NoC) that is scalable enough to support large number of elements and large bandwidth among other requirements...
The following topics are dealt with: VLSI design, automation and test; automotive electronics; GPU applications; 3D IC and analog EDA; digital baseband design; SOC platform; radio frequency; MEMS device and circuit; cloud computing; high performance processor design; BIST and DFT; and many-core technologies.
This paper proposes an innovative force-directed parallel algorithm, FDPrior, to solve the multilayer partitioning problem of 3DICs. The growing scale and multi-layered structure of the 3DIC technology make it computational expensive for EDA tools to achieve optimization goals. Exploiting the algorithmic parallelism on multi-core architectures becomes the key to attain scalable runtime. By adopting...
Through-Silicon Via (TSV) is a promising technology to reduce the length of interconnect in a three dimensional integrated circuit (3D-IC). However, the area overhead of TSV also poses a negative impact on a 3D-IC. Using too many TSVs will increase the die size and cancel out the benefit brought by TSV. Therefore, in this paper we will analyze the trade-off among wirelength and the number of TSVs...
Three-dimensional Stacked IC (3D-SIC) is a promising technology gaining a lot of attention by industry. Such technology promises lower latency, lower power consumption and a smaller footprint as compared to planar ICs. Reducing the overall 3D-SIC manufacturing cost is a major challenge driving the industry. The process of stacking the dies together is an integral part of 3D-SIC manufacturing process;...
In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss...
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