The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A 2-to-5GHz multi-phase multi-period-locked DLL is fabricated in a 90nm CMOS technology. At 5GHz, the measured rms jitter is 0.874ps and the peak-to-peak jitter is 7.56ps. The multi-phase DLL is used for a 40GHz clock generator. The core area is 0.374times0.326mm2 and the power consumption is 45mW at 1V.
The high-phase velocity (above 6100 m/s in and aluminum (Al) grating on lithium niobate (LiNbO/sub 3/)) of the longitudinal leaky surface acoustic wave (SAW) (LLSAW) mode makes it attractive for application in high-frequency SAW ladder filters in the 2-5 GHz range. We investigate the dependence of one-port synchronous LLSAW resonator performance or YZ-LiNbO/sub 3/ on the metallization thickness and...
We present results of two ultra-wideband (UWB) channel measurement campaigns in the 2-5 GHz frequency band, and use Akaike's Information Criterion (AIC) to determine suitable distributions for the channel impulse response taps. Despite the large bandwidth, AIC supports the complex Gaussian tap distribution, with mean depending on the measurement setting. We estimate the empirical covariance matrix...
This paper presents the simulation results of a conventional IFM correlator. The microwave correlator that acts as the frequency measurement mechanism of the IFM receiver was designed at 4 GHz. The structure of the correlator components such as the delay line and the Wilkinson power divider were designed to be realized in microstrip line form using the Agilent's Advanced Design System (ADS) software...
Notice of Violation of IEEE Publication Principles??A 2-5GHz low jitter 0.13 ??m CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]??by Maxim, A.in the Proceedings of the IEEE 2004 Custom Integrated Circuits Conference,3-6 Oct. 2004 Page(s): 147 - 150After careful and considered review, it has been determined that the above...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.