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An incremental delta-sigma modulator with a self-making capacitor having a high voltage operating ability for a 12-cell battery pack is proposed in this paper. The measured voltage range for each battery is from 0 to 5 V, and the maximum input voltage reaches to 60 V. The self-making capacitor adopting a metal over poly silicon with a relatively thin layer of oxide between the two plates is generated...
As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
In this work, the implementation of the chargecontrolled method in a CMOS chip is presented. The idea of the method is that the transferred total charge quantity is composed of a number of packets which are intended to stimulate the cells of the retina electrically. In addition, it will be compared with already established methods. The influence of electrode interfaces on the process is investigated...
This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv.
This paper describes the design of a serial-link transceiver that supports various communication standards from 1.25 to 12.5Gb/s, implemented in 40nm CMOS technology. Both DC and AC coupling mode can be provided by the receiver, in which a wide range PI-based CDR is also proposed. The transceiver utilizes a 3-tap FFE, a 2-stage CTLE and an adaptive 2-tap DFE to achieve the compensation for a Nyquist...
A single-event-transient-hardened-by-design (SET-HBD) charge pump (CP) is proposed to improve the reliability of the phase-locked loop (PLL) in SMIC 0.18μm CMOS process. And, the SET-HBD PLL is designed by adopting the proposed SET-HBD CP instead of the traditional CP. Simulation results show that the designed SET-HBD PLL, which is compared with the general PLL (GPLL), has better performances including...
This paper presents a 28Gbps voltage controlled oscillator (VCO) based clock and data recovery (CDR) with a separate proportional path technology. It employs a quarter rate ternary Bang-Bang phase detector to extract the phase error between the local clock and input data. The circuit designed in a 65nm CMOS process achieves ±1000 ppm lock-in rang, ±6000 ppm tracking range. The simulation results show...
In this paper, we simulate the tri-message time synchronization protocol within the cluster sub net for the MAC layer of underwater acoustic network. Distinguished with the traditional TDMA protocols, all sub nodes are time consistent with the cluster node and the sub nodes can be quickly netted in the improved TDMA protocol. We established a network simulation with a bunch of 6 nodes in OPNET software...
Most existing computer architecture simulators are cycle oriented, i.e., they are driven cycle by cycle. However, frequent switches among simulation contexts, excessive buffer accesses and tightly coupled manner often make such an architecture simulator slow, difficult to parallelize and hard to scale to large-scale many-core systems. In this paper, we propose Prophet, a parallel instruction-oriented...
This work presents a hydrogenated amorphous silicon (a-Si:H) gate driver circuit for active-matrix liquid crystal displays (AMLCDs) equipped with in-cell touch structure. The display operation can be paused several times in a frame with the horizontal blank driving method to increase the touch reporting rate. Moreover, the pre-charge structure is utilized to reduce the threshold voltage (Vth) shift...
This work proposes a new gate driver circuit which utilizes hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for high-resolution panels. By using one TFT to separate the output node from the capacitor in the gate driver circuit, the driving TFT can remain high speed to pull down the output signal. Simulation results verify that the falling time reduces over 20% without enlarging...
Stochastic circuits (SCs) offer tremendous area and power-consumption benefits at the expense of computational inaccuracies. They require random num-ber sources (RNSs) to implement stochastic number generators (SNGs) for all of their inputs. It is common for an SC to have a large number of primary and auxiliary inputs. Often the associated SNGs take up as much as 80% of the entire circuit area, so...
An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step...
This paper presents a bit-level parallel communication interface used for inter processor communication separated on different printed circuit boards. A high performance board-to-board communication interface is important in modern supercomputers and portable computers or gadgets with multiple screen displays. We propose a recalibrated transmitter and receiver soft IP cores to support asynchronous...
In this paper, we propose a high accuracy multi-chain time interval measurement (TIM) technique by employing the dedicated carry chain of FPGA. According to the principle of delay chain time to digital converter (TDC), the proposed method is realized by connecting the selectors inside the slices. The resolution of the delay chain method is limited by the time delay of one delay unit. To break through...
IEEE 802.15.4e network aims at providing highly reliable communication links via time slotted channel hopping (TSCH) technology for lossy wireless channels. In such network, all nodes remain synchronized via message exchange periodically to compensate for the clock drift. In this paper, we derive theoretical average time for a node to remain in synchronized status with its parent node under the noisy...
Clock ensembling is a promising concept for future time scale generation as robustness and stability can be considerably improved compared to master clock approaches. While ensembles consisting of the same clock types were already demonstrated to improve robustness of the generated time scale, ensembles using different clock types can clearly benefit from the advantages of the individual single clocks...
This paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint...
In this paper a complete design of a Content Addressable Memory (CAM) in bulk-CMOS 28nm technology is presented. The CAM has 64×18 bit resolution, operates at 200MHz and exploits the low power pipeline searching algorithm. Dedicated circuital solutions have been adopted to mitigate the well-known issues in CMOS 28nm-bulk technology (like higher sensitivity to Process-Voltage-Temperature variations,...
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