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We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.
A two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. Realized in 65-nm CMOS technology and sampling at 1 GHz, the prototype exhibits an FOM of 25 fJ/conversion-step while drawing 7.1 mW from a 1-V supply.
In this paper, an ultra-low power 12-bit 2 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self-calibrated. Targeted for lower noise, a low kick-back noise latch is proposed. The chip was fabricated using 0.18 μm 1P6M CMOS technology. The ADC...
In this paper, a measurement procedure with S parameters and Noise modelling for advanced MOSFET technology is presented. The complete methodology is described from the VNA (Vector Network Analyser) calibration to the simulation results using a complex de-embedding procedure. A noise measurement bench in W band (75-110 GHz) has been developed using the well known F50 method. The comparison between...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
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