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The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience...
One can run through a series of easy, virtually free changes in the closing activities to accomplish quick and substantial improvements. This chapter presents the most effective of all those free changes, which is altering the timing of closing activities. A considerable number of activities can be either partially or completely shifted out of the core closing period, either by moving them into the...
In this paper we provide a review for the time domain analysis of the normalized timing error dynamics of a wireless receiver Early-Late tracking loop (A loop that controls the timing of a pseudo-noise code that is locally generated in the receiver). This review shows that the timing error dynamics modelling is cumbersome and can be simplified by linearizing the tracking loop. The linearization assumption...
Scale Time Offset Robust Modulation (STORM) is a waveform design technique involving the simultaneous transmission of a base waveform as well as a time-scaled and time-delayed copy of that waveform. For some applications this technique is attractive as a possible candidate to enhance synchronization performance, due to the different tradeoffs of its performance properties. This paper first presents...
In this paper, we study bicasting schemes for PMIPv6 whose purpose is to achieve seamless handovers by minimizing packet loss and handover delay during a handover in a PMIPv6 domain. Bicasting schemes are able to alleviate packet loss during a handover at the expense of utilization of a significant amount of backhaul bandwidth since packets are duplicated to the current and candidate point of attachment...
Power hardware-in-the-loop (PHIL) simulation is an advanced testing method with flexibility and fidelity. A PHIL system connects power hardware or physical models under test to a real-time simulator through an interface. This paper studies the basic and general theoretic analysis of PHIL simulation. Work timing, the base of PHIL simulation, is focused and studied in detail. Based on the timing, focusing...
“Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking...
Timing analysis is a key sign-off step in the design of today's chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing...
The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical...
Two 8kbit SRAMs, one using a replica technique and the other using an inverter chain delay as timing control for word line and sense amplifiers, are simulated in 90nm CMOS technology. The stability of both SRAMs against process variations and operating conditions are compared. Results show that the bit line swing is more stable against process variations and operating conditions for the replica bit...
Despite the potential benefits of asynchronous circuits compared to synchronous circuits, only small advances have been made in the adaptation of asynchronous methodologies by the electronics industry. One of the most important reasons for that, is the lack of asynchronous Electronic Design Automation (EDA) tools and the fact that existing EDA tools are not suitable for asynchronous implementations...
The Wave Dynamic Differential Logic (WDDL) is considered as a relevant hardware countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee its effectiveness, the routing in both the direct and complementary paths must be balanced, to obtain equal propagation delays and power consumption on differential signals.
Accurate estimation of delays in Static Timing Analysis (STA) using Non Linear Delay Model (NLDM) based Look Up Table (LUT) is a major challenge in nanometer range VLSI circuits. Issues with NLDM based LUT are mostly due to the arbitrary choice of input signal transition time trin and load capacitance (Cl) and the large number of simulations to be performed for characterizing an entire standard cell...
Carbon Nanotube Field Effect Transistors (CNFETs) show great promise to become successor of silicon CMOS because of its excellent electrical properties. However, CNFET-based circuits will face great fabrication challenges that will translate into imperfection and variability and lead to significant yield reduction. In this paper, we address the timing yield problem of CNFET-based sequential digital...
FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use densely distributed test oscillators to measure within-die...
Engineering Change Order (ECO), is an effective technique for fixing circuit functionality and timing problems after the placement stage. We proposed a new approach to solve the function and timing problems simultaneously by rerouting the netlist to the spare cells. The proposed approach includes two stages (1) functional change with timing consideration and (2) timing optimization. In the first stage,...
Packet-based methods for transporting timing information are becoming increasingly important as networks shift from circuit-switched to packet-switched architectures. The packet-delay variation inherent in packet networks is a primary source of clock noise. This paper addresses suitable methods for analyzing Packet Delay Variation (PDV) and the impact on synchronization. Metrics appropriate for analysis...
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of SRAM sense amplifiers. The sense timing variation attributable to the random variation of transistor threshold voltage is reduced by sufficient count of multiple replica cells, and replica bitline delay is digitized and multiplied for adjusting it to the target sense timing. The variation...
We develop two novel globally-informed gate-sizing algorithms for tackling the problems of statistical circuit timing optimization under a timing yield constraint, and timing yield optimization under a timing (i.e., delay) constraint. Unlike previous works, our techniques are global in the sense that they use objective functions that take into account either the entire circuit's variabilities and...
Switching between line of sight (LOS) links and satellite links in an airborne network (AN) environment causes many challenging problems for the transport protocol. The typical bandwidth of a satellite link may be in the order of 1 Mbps and the round trip time (RTT) may be around 500 ms. The bandwidth of a LOS link is in the order of 300 Kbps and the RTT is just a few milliseconds. Therefore, switching...
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