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Network emulators are powerful tools that allow to test and characterize network equipment and protocols. The market offers several measurement solutions. The most widely adopted are software network emulators and among them surely free or open-source emulators are the most used especially in research contexts. Unfortunately, software network emulators are not distributed with technical support and...
Software Defined Networks provide the ability to manage networks from a centralised point through separating control plane from the data plane. This brings opportunities in terms of manageability, flexibility and cost savings in network operations. This centralisation, however, also brings about a potentially serious performance bottleneck and poses a scalability issue in high performance networks...
The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience...
In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace...
A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) during high level synthesis (HLS) is presented in this paper. To the best of the authors' knowledge, this is the first work in the literature to solve this problem. The presented approach, driven by bacterial foraging optimization...
Fault security indicates ability to provide error detection or fetching the correct output. Generation (design space exploration (DSE)) of an optimal fault secured datapath structure based on user power-delay budget during high level synthesis (HLS) in the context k-cycle transient fault is considered an intractable problem. This is due to the fact that for every type of candidate design solution...
In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
Internet has had offered plethora of services availed by the users either free of cost or at unimaginable price. Voice over Internet Protocol (VoIP) is also one of such boons provided by the net. It is a technique for transferring Voice (analog signals) over the Internet (packet switched based) using Internet Protocol (IP). Voice transmission through a non-circuit switched network rather than a dedicated...
This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers,...
Commodity hardware can be used to build a software router that is capable of high-speed packet processing while being programmable and extensible. Therefore, software routers provide a cost-efficient alternative to expensive, special hardware routers. The efficiency of packet processing in resource-constrained nodes (e.g. software routers) can be strongly increased through parallel processing with...
The paper presents a novel hardware-measurement based methodology to extract within-product-array variability as opposed to kerf. The methodology was applied to a 45nm 2.4Mb SRAM design with emphasis on critical dimension measurements. Local mismatch and spatial variations, LER effects and backend effects were measured. Lithographic models were tuned to the 45nm process. Statistically measured variability...
This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant...
This paper demonstrates reversible logic synthesis for (n, k) unidirectional logarithmic barrel shifters, where n is the number of data bits and k=log2n. The circuits are designed using only reversible fault tolerant Fredkin gates. Thus, the entire scheme inherently becomes fault tolerant. Several lower bounds on the numbers of garbage outputs and constant inputs have been proposed. The comparative...
Filtering being one of the most important modules in signal processing paradigm, this paper presents an FPGA implementation of various window-functions using CORDIC algorithm to minimize area-delay product. The existing window-architecture uses a linear CORDIC processor in series with circular CORDIC processor, that results in a long pipeline. Firstly, we replace the linear CORDIC with multiple optimized...
This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA)...
This paper presents architecture of CORDIC, embedded with a scaling unit that has only minimal number of adders and shifters. It can be implemented in rotation mode as well as vectoring mode. The purpose of the design is to get a scaling free CORDIC unit preserving the design of original algorithm. The proposed design has a considerable reduction in hardware when compared with other scaling free architectures...
With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental...
In this paper, parallel and digit-serial implementations of area-efficient 3-operand decimal adders are proposed. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient additions with three operands. Unit gate estimates and synthesis results show that our proposed adders are more area-efficient than those...
Acquisition of wide bandwidth signals is a significant problem in manufacturing test due to the cost of test equipment driven by the use of high-speed sample and hold circuitry and difficulty in data-clock synchronization. We propose to combine frequency interleaved down conversion (to overcome the bandwidth limitations of sample and hold circuitry) with incoherent undersampling (to overcome data-clock...
In this paper, in order to reduce discretization errors of dynamics with variable structures (VS), we propose an improved digital integrator. Use of Richardson extrapolation (RE) and fractional delay (FD) can improve Euler integrator, so we can obtain an improved integrator. However, Euler integrator using RE and FD directly has an infinite gain at a Nyquist frequency, and it is unsuitable for integrations...
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