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As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design...
Multiplier is one of the major hardware circuits of microprocessor and high performance systems such as digital signal processor; FIR filters, processing operations like Convolution, Cross Correlation, and auto-correlation of discrete signals, digital Image processing applications such as edge detection etc. The major design constraint of multiplier is speed which is affected due to propagation delay...
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
This paper presents the design and analysis of a 2∶1 multiplexer. The conventional circuit of 2∶1 multiplexer(MUX) is used for the calculation of different parameters like power consumption, noise, delay, leakage power, etc. The multiplexer designed in this paper is suitable for low-power applications and works on very low supply voltage. Multiplexer is a digital circuit, it consists of 2N input and...
This paper presents the design of a low leakage CMOS based switch mode power supply. The switch mode power supply converts the available deregulated A.C or D.C input supply to a regulated D.C output supply. This paper reviews the limitations of conventional linear regulated power supply and focuses on the advantages of switch mode power supply (SMPS) technique. The high frequency transformer used...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic...
This paper presents the design and performance analysis of a ring oscillator using CMOS 90nm technology. A ring oscillator contains odd number of cascaded inverter in which output is oscillating between high and low level. Inverter with minimum delay is best choice for frequency generation. Delay of inverter can reduce by adding secondary inputs and switching these earlier than the primary inputs...
Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino...
To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation...
The rapid growth in CMOS technology with the shrinking device size towards 22 nm has allowed for placement of billions of transistors on a single microprocessor chip. To achieve very high system performance, domino logic styles are widely employed in high performance VLSI chips together with aggressive technology scaling. Comparators are widely used in central processing units (CPUs) and microcontrollers...
To analysis leakage current and delay for Double Gate MOSFET with Single gate MOSFET at 45nm in CMOS Technology by using the Cadence Virtuoso simulation tool. When compared to single gate MOSFET, the leakage current and delay are observed to be reduced in double gate MOSFET. The drive current remains the same for both single and double gate MOSFET based on Vgs but the short channel characteristics...
Circuit designing using CMOS logic is the promising field for VLSI engineers, but with demand of small and portable devices, new techniques for low power are emerging. This paper proposed four different 10-T subtraction logic using Gate Diffusion Index (a new technique for low power design). Simulation results are performed using 180nm technology using Cadence Virtuoso. Complete verification for performance...
The energy efficiency and power consumption are the two primary and major concerns in present emerging applications like miniaturized bio medical sensors, pace makers, multimedia processors, etc. The energy and power consumption may decreases by multiple ways. The multiple power supply voltage design is an efficient and dominant technique for the reduction of energy and power consumption at processor...
Process variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the impact of variations in the memory cell block is the largest measured, as it is usually designed with the minimum device dimensions. Moreover, we observe a significant influence of...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
The Ex-OR and Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a full swing pass transistor based Ex-OR/Ex-NOR gate which gives better driving capability, less propagation delay and low power dissipation as compared to the existing Ex-ORlEx-NOR circuits, and by modifying...
A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic...
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