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The HEVC standard is one of the newest video coding standards developed to face the upcoming challenges concerning video processing. HEVC allows only one type of entropy encoder, which is the CABAC (Context Adaptive Binary Arithmetic Coding), responsible for the symbolic data representation in order to translate the final video bitstream to a smaller number of bits. This work presents hardware architecture...
This work presents a low-area scalable architecture for the Depth Modelling Mode 1 (DMM-1) encoder of the 3D High Efficiency Video Coding (3D-HEVC) standard, removing the refinement stage. This simplification causes a small BD-rate increase (0.09%) but a significant reduction in memory usage of 30%. The scalable architecture can support different block sizes. Synthesis results for ST 65 nm Standard...
Video coding has become widespread through mobile devices. At the same time, the adopted resolutions have been enlarged, demanding more coding efficiency and motivating the development of the new state-of-the-art standard, High Efficiency Video Coding (HEVC). However, to achieve the required efficiency the new standard greatly increased the computational intensity. That, allied to real-time constraints...
The increasing resolutions combined with storage and processing limitations of mobile devices point to the need for new compression techniques for video coding. Meanwhile, to achieve higher compression rates without compromising quality, the coding process becomes more and more complex. In reference software of HEVC the most time consuming step is the execution of Motion Estimation (ME), which is...
The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the entropy encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high...
For large-scale visual search, highly compressed yet meaningful representations of images are essential. Structured vector quantizers based on product quantization and its variants are usually employed to achieve such compression while minimizing the loss of accuracy. Yet, unlike binary hashing schemes, these unsupervised methods have not yet benefited from the supervision, end-to-end learning and...
Polar codes are a family of capacity-achieving error-correcting codes, and they have been selected as part of the next generation wireless communication standard. Each polar code bit-channel is assigned a reliability value, used to determine which bits transmit information and which parity. Relative reliabilities need to be known by both encoders and decoders: in case of multi-mode systems, where...
Dual Connectivity(DC) is one of the key technologies standardized in Release 12 of the 3GPP specifications for the Long Term Evolution (LTE) network. It attempts to increase the per-user throughput by allowing the user equipment (UE) to maintain connections with the MeNB (master eNB) and SeNB (secondary eNB) simultaneously, which are inter-connected via non-ideal backhaul. In this paper, we focus...
Energy efficiency has become a primary concern in the design of multimedia digital systems, particularly when targeting mobile devices. Approximate computing is a highly promising approach to address this challenge. This paper presents an architectural exploration in a variable block size motion estimation (VBSME) architecture using imprecise Lower-Part-OR Adders (LOA). These adders were applied to...
Now that it is becoming straight forward that industrial environments are a target for threats, hints will be provided here to face this issue with a focus on architecture and design. This approach is not treated by traditional means in detection of security vulnerabilities, like the static code analysis. Our approach explains how the quality of the code architecture against security attacks can be...
Cache memories such as magnetic ram or phase change memory came a long way in term of their architecture from their earlier models and have marked differences in power, performance, access latency, and dynamic/static energy consumption. In our work, we propose a hybrid cache design that exploits the characteristics of the employed cache technologies to achieve better power and area efficiency alongside...
We use the scattering network as a generic and fixed initialization of the first layers of a supervised hybrid deep network. We show that early layers do not necessarily need to be learned, providing the best results to-date with pre-defined representations while being competitive with Deep CNNs. Using a shallow cascade of 1 × 1 convolutions, which encodes scattering coefficients that correspond to...
Dominant approaches to action detection can only provide sub-optimal solutions to the problem, as they rely on seeking frame-level detections, to later compose them into ‘action tubes’ in a post-processing step. With this paper we radically depart from current practice, and take a first step towards the design and implementation of a deep network architecture able to classify and regress whole video...
In this paper, we discuss the architecture exploration of a Neuromorphic Signal Processing Integrated Circuit using Precise Timing. This device is intended to fulfill the role of a Digital Signal Processor in the spiking domain, becoming an essential tool to Spiking Neuromorphic Sensors such as Dynamic Vision Sensors. Our approach is based on the use of Spiking Neural Networks with preset topology...
In this paper, a novel scalable and resource-efficient architecture capable of monitoring the compressibility of a data stream with various entropy encoding algorithms is proposed. The self-adaptive architecture determines the best compression technique among many techniques which may be selected to encode an online data stream. This information can be used to reconfigure an adaptive encoding architecture...
Content-addressable memory (CAM) is the hardware based particular type of memory device utilized for low power and high-speed application. CAMs are developed for precise application without sacrificing their search speed, and it is much faster than random accessmemory (RAM) in search application. CAM executes two essential functions storing and comparing. The additional circuitry during comparison...
The scalable extension (SHVC) of the High Efficiency Video Coding (HEVC) allows encoding in layers a video with multiple quality level such as resolution, bit-depth or Signal to Noise Ratio (SNR). Compared to the equivalent HEVC simulcast, the SHVC extension provides inter-layer prediction mechanisms enabling significant bit-rate savings. Moreover these inter-layer prediction mechanisms are less complex...
This paper proposes novel soft error detection and mitigation technique in reduced instruction set computer (RISC) based pipeline processors. We leveraged the data encoding techniques (re-computing with rotated operands (RERO)) in conjunction with back pressure controlling mechanism in pipeline architecture. In order to alleviate the performance degradation due to potential stalling, we exploited...
In this paper, the high throughput hardware architecture is designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image. Even though the fixed block size motion estimation is simple with respect to the complexity of the variable block size motion estimation, variable block size estimation technique results in exquisite performance. Motion estimation is...
In this invited paper, we describe a rate-adaptive FEC scheme based on LDPC codes together with its software reconfigurable unified FPGA architecture. By FPGA emulation, we demonstrate that this class of rate-adaptive LDPC codes based on shortening with an overhead from 25% to 42.9% provides a coding gain ranging from 13.08 dB to 14.28 dB at a post-FEC BER of 10−15 for BPSK transmission. In addition,...
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