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A 60GHz patch monopole Antenna-on-chip (AoC) with a cross-shape Artificial Magnetic Conductor (AMC) is presented based on standard 0.18um CMOS process. The novel cross-shape AMC acts as a shield between the radiating element and the lossy silicon substrate. Both AMC and the patch antenna are optimized to achieve a wideband operating performance covering 57–66 GHz. The optimized AoC has a compact size...
This paper presents a compact sub-THz substrate integrated waveguide (SIW) interconnect that is designed in IBM 130 nm digital CMOS process. The footprint of the proposed SIW design is smaller than previous implementations through the application of a folded structure. The TE10 mode of the waveguide operation is excited using a current-loop excitation technique that imposes minimum layout area and...
Interdigitated back-contact solar cells with two-dimensional doping design are realized by foundry CMOS processes. Experimental results indicate superior diode performance and a 4.6% conversion efficiency that could be further boosted by thinning down the substrate.
The transmission loss of the substrate integrated waveguide (SIW) with CMOS process is investigated in this paper. It is found from the simulation and experimental results that the loss is dominated by the conductor loss other than the dielectric. The period structure of the metallic layers which is required by the CMOS process rules and the random roughness cause extra loss compared with normal conductor...
In this work we present three speed optimized types of phototransistors built in a standard 180 nm CMOS technology without process modifications. An OPTO ASIC wafer consisting of a p+ substrate with a low doped p+ epitaxial layer on top of it is used for the implementation. The phototransistors were produced in 40×40 μm2 and 100×100 μm2 sizes. A gain in responsivity of more than 13 and bandwidths...
This paper investigates the properties of the on-chip transmission lines with and without metal grounding based on measured data. Physical equivalent-circuit models are employed to evaluate the transmission lines with different ground planes, and the model parameters to predict the characteristics in the oxide layer were established and compared refer to the physical mechanism. Two different structures...
A design of barometric capacitive pressure sensor is presented in this paper, which is compatible with the standard CMOS process, and a new wafer level packaging is used to seal the vacuum cavity with a glass-silicon hybrid wafer which has a certain pattern. The electrodes of the sensor are leaded out by through silicon via (TSV) technology from back side of the silicon substrate. Mechanical characteristics...
A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65 nm CMOS process. The trigger voltage can be significantly reduced to ~3 V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin...
An area-efficient U-shaped slow-wave coplanar waveguide (U-SCPW) in a standard 0.18 μm CMOS process is presented. Compared to a conventional straight line CPW (S-CPW), it provides a more compact layout because of its approximate 1:1 aspect ratio. Measured results show that it has a quality factor and phase velocity comparable to its straight-line counterpart with measured Q ~ 30 at 23 GHz.
A wideband 60-GHz on-chip antenna fabricated with a 0.18um CMOS process with an artificial magnetic conductor (AMC) is presented. A shield plane is patterned to create mesh and inserted between the on-chip antenna and the grounded lossy CMOS substrate. With this arrangement, a frequency selective surface is produced and the meshed shield plane provides high wave impedance over a certain bandwidth...
A low-cost and high-efficiency monocristalline silicon solar cell embedded in a CMOS circuit is proposed for ULP autonomous circuits. Based on a SOI wafer, a photovoltaic lateral diode is realized in the substrate using the fabrication steps of the FD SOI CMOS process of the superposed active circuitry. In case of front side illumination, we achieve 15% efficiency when no CMOS circuit is present,...
A surface-micromachined capacitive-type micro-electro-mechanical system (MEMS) acoustic sensor with X-shape bottom electrode anchor on a Si substrate is presented. As it is designed to be implemented on only one side of a substrate for a simple monolithic integrated process, this sensor has X-shape bottom electrode anchor fabricated. The anchor operates to remove the back side process of wafer for...
Electrostatic discharge (ESD) protection for mixed-voltage I/O interfaces has been one of the major challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. Moreover, the gate leakage current across thin gate-oxide devices has serious degradation on circuit performance while circuits implementing in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage...
The paper presents a collection of slides that discusses a charge based compact model for enhancement mode PMOSFET operating in accumulation. The discussion includes silicon-on-glass substrates, RIT SiOG CMOS process, CMOS device operation, PACC model requirements, previous PACC modeling attemps, PACC model derivation (core model), PACC model results, fixed interface change, outstanding issues and...
In this work, the power-rail ESD clamp circuit fabricated in 130 nm CMOS process is investigated. In order to improve the ESD protection ability, the power-rail ESD clamp circuit with gate-substrate-triggered is proposed. By comparing with the other two techniques, gate-driven and substrate-triggered, it is shown that the secondary breakdown current of the power-rail ESD clamp circuit with gate-substrate-triggered...
This work presents the fabrication and characterization of on-chip micromachined spiral inductors in a commercially available 0.18mum CMOS process provided by TOWER Semiconductors Ltd. It explores the possibility to reduce parasitic effects and extending high frequency performance by applying a maskless micromachining post processing to create fully integrated inductors, suspended over the substrate...
In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8 V 0.18 mum standard CMOS process with high voltage boosting efficiency and little output ripple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two...
This study investigates a high Q-factor spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process. The spiral inductor is manufactured on silicon substrate using the 0.35 mum CMOS process. In order to reduce the substrate loss and enhance the Q-factor of the inductor, silicon substrate under the inductor is removed using a post-process. The post-process...
This paper presents a wideband circuit model of silicon-based interconnects for predicting their metallic and silicon substrate losses at higher frequencies. The skin and proximity effects in the structure are characterized using the partial element equivalent circuit (PEEC) method, and the parasitic parameters in silicon substrate are captured according to some analytical equations. Good agreements...
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