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Different approaches for implementing a complex multiplier in pipelined FFT are considered and implemented to find an efficient one in this paper. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The design is implemented with a focus of reducing the resources used. Some approaches resulted in the reduced number of DSP blocks and others resulted in reduced...
In this paper, a new four moduli set {2n/2 ± 1, 22n+1,2n + 1} is proposed together with a two level Chinese Remainder Theorem (CRT) based reverse converter for efficient residue number system arithmetic. The CRT is simplified to obtain a converter that is cheaper and faster than the best known state of the art converters. Experimental results obtained from FPGA implementation suggest that on average,...
Recently, OpenFlow and FlowVisor are the most promising architecture components of the software-defined networks (SDNs). The evolution of these components brought the revolution of utilizing network elements for the shared and virtual network infrastructure, however from the aspects of production networks, it still lacks of some key component. For example, policy-based services provisioning for user-defined...
This paper investigates the communication network architectures for power systems between substations using IEC 61850. Optimized Network Engineering Tools (OPNET) is used for the simulations. The simulation results show the performance of individual architectures power system communications (PSC) for substation automation systems (SASs). Nowadays, interoperability among multi-vendor substations automation...
Signal processing requires high performance digital signal processors(DSP) and hardware accelerators. Real and complex multiply-accumulate(MAC) units are the most critical computation units in the DSPs and accelerators, which greatly impact the performance, power and chip area of the signal processing system. A fixed-point Single-Instruction-Multiple-Data(SIMD)/vector MAC architecture is presented...
In recent years, much attention has been paid to wide area distributed storages to backup data remotely and ensure that business processes can continue in terms of disaster recovery. In the 'distcloud' project, authors have been involved in the research of wide area distributed storage by clustering many computer resources located in geographically distributed areas, where the number of sites is more...
Partial dynamic reconfiguration has become an important feature of FPGA-based systems as the number of applications which use this capability has increased. For systems using multiple partial bitstreams, the complexity of the target reconfigurable region, which often include heterogeneous blocks such as block RAMs and DSP blocks, makes it difficult to generate a unique bitstream which can be loaded...
The time-to-digital converter(TDC) aims to mark an accurate timestamp at the time of input signal comes. The Multi-phase Clock sampling method is an usual way to map the TDC into an FPGA. Traditionally, this method provides a medium accuracy and low resources occupation. In this paper, we present a new architecture of TDC base on the 2-ISERDES in the SelectIO, rather than utilizing the Slice resources...
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, micro processors and digital signal processors etc. A system's performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system and also it is occupying more area consuming. The Carry Select Adder (CSLA)...
In this paper, a high speed and low power 16×16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedic multiplication...
FIR digital Alters are used in Digital Signal Processing (DSP) by the virtue of its, linear phase, fewer finite precision error, stability and efficient implementation. This paper presents an architectural approach to the design of High speed reconfigurable finite impulse response (FTR) filter. In this paper new reconfigurable low power FIR filter architecture using Multiplier Control Decision Window(MCSD)...
A universal floating-point fused dot-product (UFDP) unit is presented that is capable of performing floating-point multiplication and addition or subtraction operations on two pairs of data, floating-point multiply add operation on three data items, floating-point multiplication of two data items and floating-point addition or subtraction of two data items. The proposed UFDP unit could be used as...
Utilizing Binary Signed-Digit (BSD) number representation in RNS arithmetic is called BSD-RNS. Up to the present, 2's complement BSD-RNS has been proposed. In this work, we utilize 1-out-of-3 encoding to represent residues in BSD-RNS. This paper proposes efficient modular multipliers for the moduli set {2n-1, 2n, 2n+1} based on 1-out-of-3 BSD number system. Compared to efficient 2's complement BSD-RNS...
This paper presents a low power and high speed 15-4 Compressor for digital signal processing applications. A new 5-3 compressor also proposed which is faster and also consumes less power than the conventional 5-3 compressor. This proposed 5-3 compressor is utilized in 15-4 compressor which will results in low power and high speed. Proposed 15-4 compressor is 11.01% faster and power consumption is...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
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