In this paper, a new four moduli set {2n/2 ± 1, 22n+1,2n + 1} is proposed together with a two level Chinese Remainder Theorem (CRT) based reverse converter for efficient residue number system arithmetic. The CRT is simplified to obtain a converter that is cheaper and faster than the best known state of the art converters. Experimental results obtained from FPGA implementation suggest that on average, the proposed converter is 27.96% and 21.68% better than the state of the art converter for the moduli set {2n, 2n/2 − 1, 2n/2 + 1, 22n+1 − 1} interms of area and delay, respectively. Additionally, when compared with the state of the art area and speed efficient converters for the {2n, 2n − 1, 2n + 1, 2n+1 − 1} moduli set, the proposed converter improved delay by 68.76% and 55.16% and area by 65.05% and 71.35%, respectively.