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In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We...
We consider a modified genetic algorithm that uses the two-dimensional orthogonal packing method and a block decoder for placement of the structural elements on the printed circuit board, taking into account the generalized quality criterion. Four ways are proposed to form a priority list, which determines the order of the items selection for placement.
This paper simplifies the chase decoding algorithm for TPC codes for a particular modulation scheme (BPSK). Without reducing the decoding performance, the multiplication of the new algorithm is 33% of the original algorithm. The access algorithm of receiving matrix [R] is also optimized, and the access time of receiving matrix [R] is reduced to 3%. Finally, the 800M bps TPC decoder was implemented...
A partial parallel architecture for LDPC (Low Density Parity Check Code) decoder is proposed. The overall architecture is based on MIMD (Multiple Instruction Stream Multiple Data Stream), the internal calculation unit is based on SIMD (single instruction Stream multiple data Stream). The processor uses the programmable method to realize the NMS (normalized minimum sum) decoding algorithm, can get...
In video decoder applications, motion compensation (MC) is bandwidth consuming because of the non-regular memory access. Especially with the popularity of UHD video and the development of new coding standard (HEVC), external memory bandwidth becomes a crucial bottleneck. In this paper, we propose an area efficiency cache-based bandwidth optimization strategy to minimize the memory bandwidth. First...
Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as...
An important task for training a robot (virtual or real) is to estimate state. State includes the state of the robot and its environment. Images from digital cameras are commonly used to monitor the robot due to the rich information, and low-cost hardware. Neural networks excel at catagorizing images, and should prove powerful to estimate the state of the robot from these images. There are many problems...
This work presents a comparison of two implementations of the last software version of The High Efficiency Video Coding (HEVC) decoder in a single low cost processor ARM Cortex-A series using NEON architecture which is a Single Input Multiple Data (SIMD). By using this technology of optimization, the whole execution time is reduced up to x4. We have analyzed separately all the blocks in the decoder...
Logical elements with Single-Event Transients Compensation were simulated on the base of the bulk 28-nm CMOS design rule. The result of an impact of a single nuclear particle on MOS logical gate is a noise pulse, being a single-event transient. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output state null “0” of bits error decoder...
Segment display is very important in displaying numeric data. Although matrix display can be used to show any number with better font but it has some major disadvantages compared to segment display. Matrix display uses scanning techniques to show something, this technique is complex to implement and needs more memory. Here, a 20-segment display is proposed which can show numbers and mathematical symbols...
This paper presents a novel algorithm that aims at minimizing the required decoding energy by exploiting a general energy model for HEVC-decoder solutions. We incorporate the energy model into the HEVC encoder such that it is capable of constructing a bit stream whose decoding process consumes less energy than the decoding process of a conventional bit stream. To achieve this, we propose to extend...
The brain-machine interfaces (BMIs) can establish direct communications between living brain tissue and external devices, and be applied to rehabilitate motors for disabled subjects. Considering a decoder is a key component in BMIs system, in this paper, two kinds of decoders based on the Wiener and Kalman filter are developed, and a comparison is performed to select a decoder with better performance...
This paper presents the impact of adjusting the clock frequency on our bus called Encoder-Decoder Bus System. The integrated circuits for encoder and decoder (MC145026/MC145027) are used to implement our bus system based on Arduino Uno R3 microcontroller. We consider that the clock frequency of encoder and decoder may affect to the data transfer rate between the source and destination nodes. We select...
This paper presents an economic, re-configurable, wireless communication system between two FPGAs (Spartan 3AN Starter Kit) using RF based wireless transmission at 433 MHz. This paper brings the two domains of Digital VLSI and Wireless communication, to accomplish the task of conveying data from source to destination. In this system, the 4-bit data generated at transmitter FPGA, is transmitted serially...
Now a days mobile phone has become a part of our daily life. Due to low cost of mobile phones, mobile phones are widely used for home automation. In this paper a remotely operated mobile phone controlled home appliances system is proposed. It is a DTMF (dual- tone multiple-frequency) based system consists of two mobile phones, DTMF decoder and ATmega8 microcontroller. One mobile phone is used as remote...
This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate...
This work presents an area efficient half row partially parallel pipelined LDPC decoder architecture for IEEE 802.11ad standard. It provides better area and throughput tradeoff by overcoming the low throughput bottleneck in conventional half row decoders and high complexity bottleneck in fully parallel decoders. The proposed architecture is implemented using 40-nm CMOS technology. The proposed half-row...
Model-based decision making requires prediction of future states by action-dependent state transition models. To investigate their neural implementation, mice were trained to do an auditory virtual navigation task and neuronal activity was recorded in the posterior parietal cortex (PPC) and the posteromedial cortex (PM), with the genetically encoded calcium indicator GCaMP6f after gene transfer by...
Polar codes have emerged as the most favorable channel codes for their unique capacity-achieving property. To date, numerous approaches for efficient decoding of polar codes have been reported. However, these prior efforts focused on design of polar decoders via deterministic computation, while the behavior of stochastic polar decoder, which can have potential advantages such as low complexity and...
In this work, our focus is on study and analysis of various IO standards at different temperatures. Virtex-6 is 40-nm FPGA and Kintex7 is 28-nm FPGA on which we implement our circuit to re-assure power reduction in sequential circuit. We have calculated power dissipation of different IO standards and analysed its power. The percentage of reduction in power dissipation for 28-nm FPGA is 65.56% with...
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