Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
This paper is to study the stabilizability and stabilization issues of linear dynamical systems based on the delayed and noisy feedback control. For the general linear systems, the necessary conditions and sufficient conditions for mean square and almost sure stabilizability are deduced and the corresponding feedback controls are designed according to the generalized algebraic Riccati equation. It...
This paper presents the design and analysis of a 2∶1 multiplexer. The conventional circuit of 2∶1 multiplexer(MUX) is used for the calculation of different parameters like power consumption, noise, delay, leakage power, etc. The multiplexer designed in this paper is suitable for low-power applications and works on very low supply voltage. Multiplexer is a digital circuit, it consists of 2N input and...
This paper presents the design of a low leakage CMOS based switch mode power supply. The switch mode power supply converts the available deregulated A.C or D.C input supply to a regulated D.C output supply. This paper reviews the limitations of conventional linear regulated power supply and focuses on the advantages of switch mode power supply (SMPS) technique. The high frequency transformer used...
In this paper we provide a review for the time domain analysis of the normalized timing error dynamics of a wireless receiver Early-Late tracking loop (A loop that controls the timing of a pseudo-noise code that is locally generated in the receiver). This review shows that the timing error dynamics modelling is cumbersome and can be simplified by linearizing the tracking loop. The linearization assumption...
The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic...
Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino...
Impact of line resistance variations on the crosstalk induced delay and noise is investigated in Multilayer Graphene Nano Ribbon interconnects (MLGNRs) with the help of Spectre simulations in Cadence Virtuoso design environment. Simulations are performed for intermediate and global level interconnects at both 11 nm and 8 nm technology node using latest ITRS-2013 parameters. It is found that irrespective...
Lévy noise has been employed to stabilize the differential delay system, which have generalized the Brownian motion case, and we deal with the inevitable delay problem. The sufficient conditions of stabilization and destabilization have been given in the main results, and we discuss the reasons of increasing conservatism in the final section of the paper.
Crosstalk effects in Multilayer Graphene Nano Ribbon interconnects (GNRs) are investigated with the help of ABCD parameter matrix approach for intermediate and global level interconnects at 11 nm technology node. For long intermediate and global levels of interconnects, the worst case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are far lesser than that of copper interconnects...
Nowadays the use of voice recognition system is increasing day by day. Dereverberation of speech signal is necessary to make this voice recognition system effective and smooth. Beamforming technique and an adaptive process are useful for blind channel estimation which can be used for dereverberation process. Reverberated channel estimation is a very important step for de-reverberation process. This...
Due to continued scaling of feature sizes, signal integrity and performance of today's copper based nanoscale interconnects are severely impacted. In this work, an ABCD parameter based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper based nano-interconnect systems. Using the proposed analytical model, the crosstalk delay and noise are...
The driving forces behind the need for the development of different SRAM designs are power dissipation and delay reduction along with improvement of cell stability. SRAM cell stability assessment is traditionally based on static criteria of data stability calculated through Static Noise Margin. This paper focuses on comparison of two SRAM designs by calculation of power consumption; write delay and...
Cross talk effects in large diameter Multiwalled Carbon Nanotube bundle interconnects (MWCNTs) for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate and global interconnects at 22 nm and 14 nm technology nodes. Here, isolated MWCNTs are modeled using an equivalent single conductor transmission line. Simulation results show that...
A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic...
In the proposed work, crosstalk effects are investigated in two identically coupled SWCNT bundle interconnects at 21 nm and 15 nm technology nodes for intermediate and global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse and dense SWCNT bundle interconnect system. The simulation results show that the proposed model is not only...
Single-walled carbon nanotubes (SWCNTs) have the potential to revolutionize the interconnects in future nanoscale integrated circuits. In the proposed work, crosstalk effects are investigated in SWCNTs at 21 nm and 15 nm technology nodes for intermediate as well as global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse as well as...
This paper presents a two-path design of quadrature band-pass modulators and discusses the architectural level implementation issues for power reduction. The methodology uses an architecture which locks IF frequencies to the sampling frequency. The basic delay based solution is converted into integrator based solution for the implementation. Robustness of the structure against the mismatch...
Frequent episode mining has been proposed as a data mining task with the goal of recovering sequential patterns from temporal data sequences. While several episode mining approaches have been proposed in the last fifteen years, most of the developed techniques have not been evaluated on a common benchmark data set, limiting the insights gained from experimental evaluations. In particular, it is unclear...
Due to increase in Vt (threshold voltage) variation caused by global and local process variations in ultrashort-channel devices, CMOS-based 6T SRAM cell and its variants cannot be operated at voltage lower than 600 mV. Therefore, this paper presents a FinFET-based 8T SRAM cell to mitigate impact of process variation. In this work, various design metrics are assessed and compared with MOSFET-based...
It is known that signal acquisition can be treated as a two-dimensional search and all the possible results are located in the search plane as different cells. In this paper, the theoretical expression of the cross-ambiguity function (CAF) is analyzed, and the property of the approximate expression is exploited, while it is seldom addressed in previous GNSS receiver architectures. Based on the property...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.