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In the past several decades on-chip dimensions have scaled over 2000X, while dimensions on printed circuit board have scaled 4-5X. This modest scaling of packaging dimensions has severely limited system scaling. To address this, we have proposed a disruptive package-free integration scheme. We replace the traditional organic printed circuit board (PCB) with silicon interconnect fabric (SiIF) and replace...
2.1D package technology (chip on substrate) as a potential low cost solution for 2.5D silicon interposer package (chip on wafer on substrate), we develop here a panel type manufacture organic interposer (scheme 1). 2.1D technology focus on the production cost and the ball count range which defined by line/space. We presents the demonstration of high resolution photolithography semi-additive processes...
A tunable aperture using a metal expansion by Joule's heating which operates when the voltage is applied to two copper metal structures having high thermal resistance is proposed. This aperture has four thermal actuators that can obtain 3D image and distance information in a single camera. The proposed thermal actuator is based on two slightly bent beams that can actuated in directed direction and...
This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical,...
This paper focuses on the influence of annealing process on the properties and microstructural evolution of through-silicon-via electroplating copper. Particular attention is paid to the interposer-related through-silicon-via applications, which is fabricated by via-last process with the diameter of 20 microns and above. A interposer was designed and fabricated with its diameter of 100 microns and...
Via last TSV (through silicon via) technology is more and more applied in 3D WLCSP, which can decrease package volume and increase I/O density. The process of via last includes temporary bonding, grinding, photolithograph, silicon etching, SiO2 etching, CVD, PVD, plating and so on. Silicon etching and SiO2 etching are important process of via last TSV package for interconnect technology. Temporary...
Silicon anodes, with an extreme high theoretical specific capacity of 4200mAh g−1 and proper stable plateau potential of 0.4V, are considered one of the most promising anode materials in rechargeable Lithium-ion batteries. However, the great structural and volumetric changes during charge/discharge cycles relating to poor cycling performance are still the most critical challenges limiting the breakthrough...
High bandwidth Package on Package (HBPoP) had be well used which replaced FCMAPPOP in high-end mobile products with its advantages of wide I/O counts, high performance and the better integration between application processor and stacked memory packages. The structure of HBPoP is utilized flip-chip technology with ball grid array (BGA) balls on the bottom package and connect top DRAM package with substrate...
In this study, a comparison of the interfacial adhesion strength of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon nitride (SiN)/Cu and High-Density Plasma Chemical Vapor Deposition (HDP CVD) SiN/Cu was performed using the 4-Point-Bending (4PB) technique. Differences in critical energy release rate value Gc, which is an indicator of the interfacial adhesion strength, were observed. The...
This paper reports the development of electrically conductive, polymer nanofibers fabricated by electrospinning and electroless copper plating. The electrospun nanofibers were made using a precursor consisting of styrene-isoprene-styrene (SIS) block copolymer and silver trifluoroacetate. For process development and materials characterization, the fibers were electrospun as a thin membrane on glass...
In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small...
A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye...
This paper presents, for the first time, a novel silicon damascene like via-in-trench (ViT) interconnect for panel-scale package redistribution layer (RDL) configuration. The panel scale damascene RDL in this paper comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry film photosensitive dielectric. A 140 µm thick glass substrate...
In this paper, the pumping behaviors of copper filler from TSV were systematically investigated. First, in-situ observation of copper pumping from TSV was conducted in scanning electronic microscope (SEM), the pumping height of copper filler and its evolution with time and temperature was recorded, it is found that the pumping rate increase with temperature and the maximum pumping height reached 12...
Silver (Ag) has been emerging as an attractive die-attach material for high power devices because of its highest thermal conductivity among metals and high melting stability. The most well-known silver die-attach technique is to sinter micro-or nano-silver pastes. The challenging issues of sintered Ag joints are pores in the joint and migration of unfriendly species such as chlorine ions through these...
Handheld consumer electronics are requiring more complex packaging designs to accommodate higher component densities and reduce form factor. Fan-out wafer-level packaging (FOWLP) has garnered much attention lately as a cost-effective way to achieve high interconnect density and manage larger I/O counts within an affordable package. Two principal approaches to manufacturing FOWLP components have evolved:...
Emerging fan-out packages require advances in mold compounds, polymer interfaces to metals and silicon, and innovative processing to reach the required high reliability. In this paper, we discuss the fracture energy for mold compound interface to copper and silicon, and use that information for studying interfacial delamination propagation of mold compound. We have examined mold compound delamination...
Reliability analysis is performed for various redistribution layer (RDL) interconnect patterns. Five different RDL patterns are designed to examine die pitch, line length, line width, dummy block, and die edge/corner effects on RDL reliability. Temperature dependent material properties, grain growth induced stress, thermal mismatch stress, and plastic deformation evolution are taken into consideration...
In this article we present the conception, technological fabrication and electrical characterization of 3D hybrid pixel detector modules based on read out chips (ROCs) with through silicon vias (TSVs) which are flip chip bonded onto silicon photon sensors for X-ray detection. The TSVs in the ROCs enable a vertical routing of their peripheral IOs to the back side where they are spread to a land grind...
Silicon Interposers enable very high routing density in between integrated circuits (ICs) that are fabricated in different technologies like 65 nm for power amplifiers and 14 nm FinFET for highest performance. This is not possible within a System on Chip (SoC). While heterogeneous silicon interposer integration is now used in the first products for processor-memory-integration, it is still rarely...
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