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This paper examines the problem of generating testing actions for electronic industry test systems designed for verification of electronic packages of UHF band. This paper shows complex problems of setting amplitude and time parameters of multichannel generators of test signals. The problems of multichannel wide range signal generation and frequency control, rise and fall time control, pulse time...
Ensuring accurate testing of a UHF electronic package is the main requirement for a testing system. There are two problems: metrological certification as generator devices generating test pulses of desired amplitude and at a desired moment of time and the problem of measuring amplitude and time parameters of signals at the outputs of an electronic package. This paper observes the methods of measurement...
The paper describes the dependence of the SEU cross-section on the clock frequency for a CMOS 0.18um microprocessor's test chip. An attempt has been made to find the relationship between the parameter of the minimum supply voltage and the frequency dependence of the SEU. Original experimental results are obtained.
Many analog and mixed signal devices have very few or no digital pins. In spite of this, these products can be highly complex internally, including significant digital content. They may contain various sensors and control circuitry, which react to a variety of conditions to control the power profile of the part and its environment. These factors can make these devices very challenging to test. They...
Spectral testing and linearity testing are two important categories in ADC testing. The sampling clock quality is a crucial factor in ADC spectral testing. The cumulative clock jitter of the sampling clock generates power leakage in the fundamental component of the ADC output spectrum, and the random clock jitter increases the noise floor of the ADC output spectrum, which corrupts the spectrum result...
With recent advances and demands for data storage, new architectures for data controller chips are picking pace. Accordingly, the test methodologies for such chips are also becoming crucial since the large shipping volumes of those chips demand very few field returns. Along with the advances there is a need for a robust test strategy with some novel techniques which can be enabled to test the SOC...
A novel 2-stage testing structure for CMOS pixel sensor (CPS) is proposed here. The test stimuli are based on applying the electrical pulses instead of light stimuli on photosensitive area, for pure electrical test. The voltage stimuli applied is generated by charge-pump phase locked loop (CP-PLL) which is used here as on-chip clock, exploiting the dual role. Existing charge-pump circuit as stimulator...
Nowadays, single event upsets (SEU) and the occurrence of delay faults caused by manufacturing defects are significant problems in high density VLSIs. Thus, researchers have drawn great attention on SEU tolerant design and delay fault testing. In this paper, two novel slave latches and a master latch have been proposed to improve the SEU tolerance of a flipflop in scan delay testing. The main purpose...
A 12-bit 32nm SOI CMOS pipeline ADC clocked at 200 MSps was tested at LBNL with the MilliBeam™ technique and showed no upsets with LET up to 30.9 MeV·cm2/mg (Kr), while 1-sample SETs up to 600 LSB in amplitude were observed with broad-beam exposure at TAMU with 0°, 60° incidence angles (Xe and Au), and LET up to 170 MeVcm2/mg.
We performed proton and heavy-ion testing of the Microsemi Igloo2 FPGA using several basic designs looking at the logic, embedded SRAM, and mathblocks as well as any SEFI or high current states.
Single Events Effect (SEE) characterization results for LVPECL 1:10 Clock Distributor is summarized, showing very robust SEE performance up to LETeff=69.2 MeV-cm2/mg.
Verification takes on a much greater importance in secure and reliable System-on-Programmable-Chip (SoPC) systems. A set of verification methods, containing static analysis and configuration-level simulation, is implemented and applied to a typical SoPC system in this paper. Static analysis methods are illustrated in detail, such as Coding-Style analysis, Clocking-Domain Crossing (CDC) analysis, and...
This paper presents a new scan-based at-speed test signal scheme called One Clock Alternated Shift (OCAS) for minimizing the potential impact of the power distribution network PDN impedance variation. The strategy behind this new scheme is to mimic the clock signal of the functional mode as closely as possible. As a case study, we consider the PDN impedance variation that can occur with 3-D ICs, more...
Precise control of synchronous drive depends on the accurate position feedback of the rotor. This can be achieved using an absolute position encoder. One of the protocol used for encoder is Synchronous Serial Interface. The encoder with this protocol has to be interfaced with the drive or the testing setup in laboratory. In order to avoid a physical hardware, this paper proposes the SSI protocol implementation...
This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle...
A method for separating and accurately estimating ADC noise, aperture jitter, and clock jitter is presented for ADC testing and characterization. This significantly relaxes clock jitter requirements and removes the need for high precision test instruments, but still allows ADC specifications like SNR, SNDR and ENOB to be accurately estimated.
In the context of use-case centric development and requirements-driven testing, this paper addresses the problem of automatically deriving system test cases to verify timing requirements. Inspired by engineering practice in an automotive software development context, we rely on an analyzable form of use case specifications and augment such functional descriptions with timed automata, capturing timing...
Testing using architectural design models is intended to determine if the realized system meets its specification, and works as a whole in terms of computational components and their interactions. The growing complexity of embedded systems requires new techniques that are able to support testing of extra-functional requirements, like energy usage of components and systems, which is very necessary...
Model-based testing is a well-known technique for automating the otherwise tedious process of testing. Test cases are automatically created from a formal model, according to some test criterion which determines when the test suite is complete. In model-based mutation testing, the test criterion is defined via faulty models, called mutants, which are used to create test cases that specifically target...
The switching activity due to various test vectors has direct effect on amount of power consumption during testing. Due to higher switching activity during test mode compared to the switching activity during functional mode the power consumption may be higher than functional mode power consumption. The excessive average and instantaneous power requirement during slow speed and high speed test conditions...
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