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Integrated circuits based on low supply voltage and subthreshold operations of NMOS devices are very attractive for low power applications. An effective way to reduce supply voltage and resulting in power consumption without losing the circuit performance of NMOS is to increase the drive current of NMOS. This paper reports the scaling analysis of NMOS from deep-submicron to nanometer technologies,...
This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45??-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current...
High energy borane (B2H6) gas cluster ion beam (GCIB) successfully enables a sub-10 nm box-shaped dopant profile without channeling tail, and steep gradient (2.5 nm/dec) in lateral direction. pFET using GCIB source/drain extension shows superior suppression of short channel effects and reduces the dependency of drive current on gate overlap capacitance variation for scaled devices. Moreover, the perimeter...
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