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We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.
We cannot improve what we cannot measure and a major issue with system test today is that we do not know how effective it is in detecting defects, diagnosing failures, and ensuring field quality. This situation is in contrast to that of ICs, where test quality metrics have resulted in DPMs of 100 -1000 at board and system test and mean time to failures in the hundreds of millions of hours. This paper...
A methodology using design-for-manufacturability (DFM) layout guidelines as a basis for modeling and detecting systematic defects was proposed earlier. In this paper, we show that this methodology can be extended to prioritize layout locations according to the importance of applying DFM guidelines to them. Prioritization is done based on test considerations including coverage and test set size. In...
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