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In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
This paper describes the design and measurement results of a supply modulator for a PA for GSM, EDGE and UMTS application. The modulator combines a high-bandwidth class-AB linear regulator with an efficient DC/DC converter in a master-slave configuration. The DC/DC converter is current-mode controlled and has been designed to operate at switching frequencies between 1 MHz and 25 MHz. A damped dual-inductor...
A 0.9-V input discontinuous-conduction-mode (DCM) boost converter delivering 2.5-V and 100-mA output is presented. A novel low-voltage pulse-width modulator is proposed. The modulator can be directly powered from the 0.9-V input instead of using the 2.5-V output as in general modulator designs. Sophisticated low-voltage analog blocks, which normally consume a large amount of power and chip area, are...
This paper describes the design and measurement results of a 1-bit A/D converter based on a transistor only switched current (SI) second order sigma-delta modulator. The 1-bit A/D converter was simulated and processed in ES2 1.5 ??m CMOS technology. The second order filter is based on class AB current-integrators. Measurement results on the first silicon show this circuit technique promissing for...
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