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Novel applications demand computational resources that are provided by multiprocessor systems-on-chip (MPSoCs). At the same time, they increasingly process sensitive data and incorporate security-relevant functions like encryption or authentication. This paper discusses the implications of the MPSoC technology on security. It provides an overview of hardware-oriented techniques to enhance security...
Systems-on-Chips (SoCs) are one of the key enabling technologies for the Internet-of-Things (IoT). Given the continuous distribution of IoT devices, data confidentiality and user privacy are of utmost importance. However, with the growing complexity of SoCs, the risk of malware infections and trojans introduced at design time increases significantly. A vital threat to system security are so-called...
The emergence of Internet-of-Things has imposed more stringent security requirements on SoC devices. Basic security requirements include confidentiality and integrity, which imply less observability and controllability of the SoC from the outside world. On the other hand, observability and controllability are essential to SoC debug activities. Without bearing in mind the conflicting nature of security...
Fragmentation of the system-on-chip supply chain has introduced many vulnerabilities in electronic devices. A proposed platform solution lets supply-chain participants authenticate, track, provision, and analyze their products during the entire chip life cycle through a single root of trust in the form of unique chip IDs.
This paper briefly presents a position that hardware-based roots of trust, integrated in silicon with System-on-Chip (SoC) solutions, represent the most current stage in a progression of technologies aimed at realizing the most foundational computer security concepts. A brief look at this historical progression from a personal perspective is followed by an overview of more recent developments, with...
With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH)...
Hardware Trojans compromise security by invalidating the assumption that hardware provides a root-of-trust for secure systems. We propose a novel approach for an FPGA system-on-chip (SoC) to ensure confidentiality of trusted software despite hardware Trojan attacks. Our approach employs defensive techniques that feature morphing on-chip resources for moving target defense against fabrication-time...
As demonstrated by the recent attack on Intel's Ivy Bridge processor, the traditional Logic Built-In Self-Test (LBIST) methods do not provide adequate protection of SoC against malicious modifications known as hardware Trojans. In this paper, we introduce a simple but efficient countermeasure against hardware Trojans which exploits non-zero aliasing probability of LBIST. We propose to generate LBIST...
In the complicated application environment, for example, the distributed system, attackers using various illegal ways to attack the Field Program Gate Array (FPGA) devices to destroy or forge the hardware logic and the firmware. This paper proposes a feasible method which provides a FPGA chip with configuration interface, control and check interface. Through building a trusted channel with this FPGA...
Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology...
This paper presents a scalable and flexible multi-core SoC architecture for high-speed key exchange for emerging IP security systems. Novel approaches are proposed for HMAC authentication block parallelization, distributed key handling and a pipelined block cipher design that allows feedback encryption modes. This improves upon previous state-of-the-art designs for IPSec, creating an architecture...
Embedded platforms are becoming increasingly more resource-rich (e.g. processing speeds, number of cores, memory, and communication rates). As a result, they are being transformed from `closed', fixed-function devices to programmable and flexible platforms capable of supporting diverse types of services. One approach to enabling service diversity jointly with proper isolation of key critical functionality...
Because the speed degradation and on-chip resources limit large CAM applications on SoCs and FPGAs, Hash-CAM architectures are attractive concepts combining the space efficiency of hashing algorithm and fast lookup character of the CAM for collision resolutions. In proposed Hash-CAM circuit, single and double hashing schemes are explored and compared. It proves that, with parallel CRC circuit and...
In a highly connected world, security in networks is still a significant challenge for researchers. However, cryptographic algorithms are computationally intensive and a number of security schemes have recently emerged intended to overcome the limit processing and power resource. The processors used in Field Programmable Gate Array (FPGA) embedded systems are known to have a modest performance. This...
Based on the analysis of the round transformation and key expansion, the advanced encryption standard (AES) algorithm is optimized through the look-up table. And then the optimized Rijndael algorithm based on SOPC (system on a programmable chip) is designed and implemented through software and hardware. According to the software design flow chart of the optimized Rijndael algorithm, the program design...
Nowadays, systems-on-chip are commonly equipped with reconfigurable hardware. The use of hybrid architectures based on a mixture of general purpose processors and reconfigurable components has gained importance across the scientific community allowing a significant improvement of computational performance. Along with the demand for performance, the great sensitivity of reconfigurable hardware devices...
In this paper, we design and implement a cryptosystem SoC (CSoC). We combine a virtual microprocessor and AMBA bus to elaborate an embedded system model that is capable of shortening the testing time of the global system and calculating the performance for various types of microprocessors. The virtual microprocessor instead of the physical one is used to control the entire system, so that the high...
Software intellectual property (SWIP) is a critical component of increasingly complex FPGA based system on chip (SOC) designs. As a result, developers want to ensure that their SWIP sources are protected from being exposed to an unauthorized party and are restricted to run only on a trusted FPGA platform. This paper proposes a novel design flow for protecting SWIP by binding it to a specific FPGA...
Modern system-on-chip (SoC) designs rely heavily on reusable, verified and bug-free hardware intellectual property (IP) cores. Recent trends of IP piracy and reverse-engineering are causing major revenue loss to the IP vendors. A large majority of hardware IPs comes in register transfer level (RTL) description due to their portability and flexibility to map to any technology platform. In this paper,...
This paper proposes a method for measuring hardware configurations for trusted platforms based on field programmable gate arrays (FPGA). The proposed system setup allows for partial reconfiguration as well as full reconfiguration of FPGA devices that can be used additionally as trusted platforms. In the system, slots are defined for fast partial dynamic reconfiguration. Predefined IP blocks may be...
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