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A monolithic switched-capacitor voltage converter to drive the virtual VSS for low standby power “drowsy” modes is presented. The voltage converter has been fabricated on a 0.13-µm digital CMOS process. Test chip measurements demonstrate current drive capability from 10 µA to 100 µA with power efficiency over 86%. The test chip measurements also demonstrate that the chip level power efficiency of...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
A tunable/adaptive feedthrough-error cancelation technique for switched-current circuits is presented. A comparison, based on measurements from silicon prototypes designed with the same technology and equal geometries, shows an improvement of more than one order of magnitude as compared to the conventional dummy-switch technique. Robustness against local process or switch-geometry variations has been...
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