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Modern patient data tends to be large-scale and multi-dimensional, containing both spatial and temporal features. Learning good spatio-temporal features from large patient data is a challenging task, especially when there are missing observations. In this paper, we propose a spatio-temporal autoencoder (STAE), an unsupervised deep learning scheme, to learn features from large-scale and high-dimensional...
This paper presents an energy-efficient solution to overcome packet loss in Wireless Sensor Networks (WSNs) by adding seed-based Random Linear Network Coding to MQTT for Sensor Networks (MQTT-SN). Whereas most sensors integrated in common WSN devices consume little energy, using the radio is costly. To increase battery lifetime, devices try to minimize their radio uptime, while still satisfy timeliness...
The 10Gbase-KR protocol is widely used to accomplish the high speed data conversion in the Ethernet area. This paper presents a design of the critical controller in the physical coding sublayer based on the 10Gbase-KR. In order to satisfy the demand of the high speed data conversion, the scrambler and descrambler are specially designed to work in a parallel mode. The post-synthesis simulation results...
In this paper we introduce and evaluate Haar based codec assisted medium and long range data transport structures, e.g., bus segments, Network on Chip interconnects, able to deal with technology scaling related phenomena (e.g., increased susceptibility to proximity coupling noise and transmission delay variability), targeting energy savings at the expense of a reasonably small overhead, i.e., 1 extra...
In this paper we present a new architecture for thermometer-coded digital-to-analog converters (DAC) that are used as a part of segmented DACs. The size of the binary-to-thermometer decoder tends to grow relatively large compared to the DAG when the number of input bits increases. We propose an architecture that utilizes PMOS current source transistor and moves the switching logic inside the current...
Training convolutional networks (CNNs) that fit on a single GPU with minibatch stochastic gradient descent has become effective in practice. However, there is still no effective method for training large networks that do not fit in the memory of a few GPU cards, or for parallelizing CNN training. In this work we show that a simple hard mixture of experts model can be efficiently trained to good effect...
Effective integration of local and global contextual information is crucial for dense labeling problems. Most existing methods based on an encoder-decoder architecture simply concatenate features from earlier layers to obtain higher-frequency details in the refinement stages. However, there are limits to the quality of refinement possible if ambiguous information is passed forward. In this paper we...
Attention-based neural encoder-decoder frameworks have been widely adopted for image captioning. Most methods force visual attention to be active for every generated word. However, the decoder likely requires little to no visual information from the image to predict non-visual words such as the and of. Other words that may seem visual can often be predicted reliably just from the language model e...
With the rise and popular of artificial intelligence,the technology of conversation between human and machine get more and more attention. Using neural network model on the Encoder-Decoder framework has been wildly used in translation and human-machine conversation. This paper we propose a new hybrid neural network model (HNN) which consists of some essential neural network models (that is RNN, LSTM,...
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix...
We introduce a stochastic resonance based decoding paradigm for quantum codes using an error correction circuit made of a combination of noisy and noiseless logic gates. The quantum error correction circuit is based on iterative syndrome decoding of quantum low-density parity check codes, and uses the positive effect of errors in gates to correct errors due to decoherence. We analyze how the proposed...
Partial reconfiguration (PR) of a reconfigurable fabric is typically performed at run-time at the level of a "frame" (the smallest independently reconfigurable unit). Large frames often cause many elements to be reconfigured unnecessarily, causing the partial reconfiguration time to increase. While reconfiguring a large number of small frames, reduces the number of configuration bits used,...
Network-on-Chip (NoC) is basic part of given system. It is substitution for System-on-Chip to decrease the complexity. Large numbers of different data packets are sent at a time through different links, known as parallelism. But instead of degrading the performance, NoC keeps on growing in performance and scalability. In nanometer CMOS technology, interconnection of links dominates both performance...
Traditionally, DFT patterns exacerbate dynamic power consumption in large ASICs. At-speed scan and memory tests are sensitive to voltage droop and peak current because the power grid is designed for functional power viruses (maximum workload applications) whose power consumption is much lower than DFT patterns. Our goal in this work is to ensure that the quality of test is not compromised while power...
Reversible logic is the emerging field for research in present era. The aim of this paper is to design and synthesize a Programmable Read Only Memory (PROM) using a reversible decoder which is designed using reversible logic with minimum quantum cost. The PROM is a Programmable Logic device which consists of fixed AND Gates and programmable OR gates array. Fixed AND gates can be termed as a decoder...
Reversible logic is the emerging field for research in present era. The aim of this paper is to design and synthesize a Programmable array Logic (PAL) and Programmable Logic array (PLA) using reversible logic with minimum quantum cost. The PAL is a Programmable Logic device which consists of programmable AND Gates and fixed OR gates array. The PLA is the PLD which contains programmable AND array and...
We propose a technique that reduces static power consumption in caches with negligible hardware overhead and no performance penalties. Our proposed architecture achieves this by deterministically lowering the power state of cache lines that are guaranteed not to be accessed in the immediate future by exploiting in-flight cache access information. We simulated our architecture using the Simple scalar...
In recent trends of VLSI technology the reversible logic has became the major area of research in optimization of area, power and speed constraints. The reversible logic has equal number of inputs and outputs. In wireless communications Viterbi algorithm is employed to have minimal number of communication channels. The Viterbi decoder design at 65nm technology using reversible logic has made an attempt...
High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density...
This work presents the design of a Morse decoder implemented using fourteen different architectures described in Verilog. All designs are synthesized in FPGA and ASIC, using Xilinx ISE and Vivado for the former and Leonardo Spectrum and Design Compiler for the latter. The performance and resource requirements after synthesis of each architecture are compared to gain insight on the impact caused by...
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