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In this article a brief description of a direct conversion receiver is given, sources of affected channels in such a receiver are examined. Practical methods for eliminating of affected channels of a real radio system are proposed.
Random numbers are critical in every cryptographic fields. They can be used as cryptographic key, seed, nonce, initialization vector, etc. In this paper, new (pseudo) random number generator (PRNG or RNG) based on computer's source is proposed. The principle of method consist in collecting (nearly) random sources produced from computer and used it as seed for (pseudo) random number generation. Random...
This paper examines the problem of generating testing actions for electronic industry test systems designed for verification of electronic packages of UHF band. This paper shows complex problems of setting amplitude and time parameters of multichannel generators of test signals. The problems of multichannel wide range signal generation and frequency control, rise and fall time control, pulse time...
A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
This work presents an area-efficient voltage and frequency scalable clock generator for low-power digital SoC clocking. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1V with measured jitter from 1.7% to 5.1% UI. Its low power consumption of 0.40pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency...
Ensuring accurate testing of a UHF electronic package is the main requirement for a testing system. There are two problems: metrological certification as generator devices generating test pulses of desired amplitude and at a desired moment of time and the problem of measuring amplitude and time parameters of signals at the outputs of an electronic package. This paper observes the methods of measurement...
This paper presents a low-power adaptive edge decision feedback equalizer (DFE) for 10 giga-bits-per-second (Gbps) serial links with 4 PAM (pulse-amplitude-modulation) signaling. Optimal tap coefficients are obtained adaptively using a sign-sign least-mean-square (SS-LMS) algorithm that minimizes the jitter of equalized data. Low-voltage-differential-signaling (LVDS) tap generators that double DFE...
This paper presents a multi-purpose built-in selftest circuit to reduce large design overhead in preparing various tests of high-speed links. The proposed circuit can be configured as a pattern generator, a pseudo-random bit sequence generator, a scrambler, a descrambler, or a snapshot, all of which are frequently used in various link tests but also require significant design effort. T o reduce the...
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks,...
A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of...
Annotation — This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (THPN). The implementation...
To achieve high availability in the face of network partitions, many distributed databases adopt eventual consistency, allow temporary conflicts due to concurrent writes, and use some form of per-key logical clock to detect and resolve such conflicts. Furthermore, nodes synchronize periodically to ensure replica convergence in a process called anti-entropy, normally using Merkle Trees. We present...
Miniaturized voltage sensors (electrodes) implanted into the brain tissue are capable of recording the brief electrical impulses (spikes) of neurons located close to the electrode sites. To investigate the activity of individual neurons and discriminate spikes generated by different neurons a technique called spike sorting can be applied on the recorded data. However, the performance of current spike...
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked...
A scan-based side-channel attack is still a real threat against a crypto circuit as well as a hash generator circuit, which can restore secret information by exploiting the scan data obtained from scan chains inside the chip during its processing. In this paper, we propose a scan-based attack method against a hash generator circuit called HMAC-SHA-256. Our proposed method restores the secret information...
A method to synchronize a group of microcontrollers with different clock frequencies of their own generator is proposed. The algorithm of each microcontroller operation in the group and the block diagram of the group consisting of N microcontrollers are presented. Timing diagrams of signals of synchronous operation and clock pulses of the microcontrollers group are given. The result of the work, at...
This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation...
Stochastic circuits (SCs) offer tremendous area and power-consumption benefits at the expense of computational inaccuracies. They require random num-ber sources (RNSs) to implement stochastic number generators (SNGs) for all of their inputs. It is common for an SC to have a large number of primary and auxiliary inputs. Often the associated SNGs take up as much as 80% of the entire circuit area, so...
This paper presents an open-loop 28GHz 16-phase clock generator in 28nm CMOS technology. The open loop architecture is composed of 22.5° delay units and uses phase compensation to account for delay time variations. The 16-phase 28GHz clock generator consumes 14mW, leading to a power efficiency of 0.032mW/GHz/phase. The maximum phase error is 6° and the RMS phase error is 3° when the input frequency...
IEEE1588 (PTP: Precise Time Protocol), which aims for the sub-microsecond range of clock synchronization in a minimal network, is currently focused on highly precise clock synchronization. Boundary Clock (BC) and VLAN Priority are considered to be features that improve PTP accuracy. Although some papers addressed the accuracy, these evaluations were realized using different evaluation metrics and...
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