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Power consumption in a digital circuit increases significantly during test mode. The paper proposes a novel technique to minimize the peak power by circuit clustering based on distribution of energy among the scan cells. All the clusters are equally compatible with respect to the number of scan cells and total system energy which is equally divided among the clusters. The final energy of the system...
Design for Test (DFT) introduces certain elements such as buffers, inverter-pairs etc, though inconsequential, are integral part of a digital design. However, while debugging a circuit schematically, they waste precious real estate when a designer is mostly interested in the logical design elements. At the same time, it is important that these inconsequential elements are not discarded altogether...
This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to determine tree topology, and a Voronoi diagram to establish physical connections. It achieves higher test data compression and far lower test application time,...
Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of...
Recent studies have shown that new tests are required for the detection of a large percentage of scan cell internal open faults which are not detected by the existing tests. However, the additional coverage due to the new tests drops significantly when opens with moderate resistances are considered. In this paper we propose to augment earlier test methods to detect internal scan chain opens with a...
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the errors in responses due to defects which are captured in scan cells are not directly observed. We propose a simple and effective way to enhance the diagnostic resolution achievable by production tests with minimal increase...
This paper proposes a novel power-aware scan architecture: DCScan. In this architecture, the compatible scan cells are grouped into the same segment. Test data propagation in DCScan includes two parts: data copying and data shifting. There is no scan shift-in transition during data copying. Experimental results show our approach can achieve low test power, low wiring overhead and low test response...
In many designs asynchronous inputs are used to set and/or reset flip-flops. Considering a scan cell implementation used in an industrial design we show that stuck-open faults in some transistors driven by asynchronous inputs require two new flush tests. Such faults, if left undetected, cause functional failures. The two new tests increase the overall stuck-open fault coverage of each scan cell by...
This paper presents a scan-based DFT technique that uses limited number of enhanced scan cells to reduce volume of delay test patterns and improve delay fault coverage. The proposed method controls a small number of enhanced scan cells by the skewed-load approach and the rest of scan cells by the broadside approach. Inserting enhanced scan cells reduces test data volume and ATPG run time and improves...
We present low power illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modifying the clock tree of the design. The proposed architecture is independent of the ATPG patterns and...
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of manufactured chips. In this paper, we propose a set of techniques that enable the accurate pinpointing of hold time violating scan cells, their modeling and tolerance, paving the way for the generation of valid test data that...
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