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A semiconductor floating gate structure nonvolatile memory chip with a control gate, which was invented by the author in 1970, is becoming mainstream as a prototype of flash EEPROMs among other types of memory chips. In this paper, the author will provide a history of the development of nonvolatile memory, discuss its position as a memory device, and discuss the operation principles and configuration...
The paper demonstrates that H atoms diffused into the CVD tunnel oxide degrade the endurance of split-gate type flash EEPROMs. The authors observed that F-N stress application generates high trap densities at the tunnel-oxide/FG interface as well as negative charges in the tunnel oxide. The density of FN-induced traps and charges was found to strongly depend on the liner nitride (SiN) film quality...
Oxides used in EEPROMs have severe limitations placed on leakage currents due to long data retention time requirements. During write/erase (W/E) cycling, traps, responsible for both decreased tunneling currents and increased stress-induced leakage currents (SILCs), are generated inside the tunnel oxides. The decreased tunneling currents impose endurance limitations. The increased SILCs are partially...
A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM...
A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation...
A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage...
A full 4-Mb flash EEPROM was fabricated in 0.8-μm CMOS and its functionality was verified. Conservative 1.0-μm features were used in the periphery, resulting in a die area of 95 mm2. The device features 5-V-only operation and either full-chip or sector erase. A segmented architecture, remote row decode, and innovative design techniques provide the sector erase feature and high-voltage...
An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described
A 1-Mb flash EEPROM (electrically erasable and programmable read-only memory) with a 5.6- mu m*4.4- mu m cell is fabricated with a double-polysilicon, single-metal, n-well CMOS process. A double-diffused drain structure is used to reduce hot-electron degradation of n-channel peripheral devices. The memory is organized into 1024 rows and 128 columns for each output. Erase and programming operations...
The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and...
A contactless cell array technology has been developed for a single-power-supply 5V-only CMOS flash EEPROM (electrically erasable programmable read-only memory). The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM test vehicle. This low-current approach has been realized with cell area and cost comparable to those of the recently reported dual-power-supply...
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