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Two new switched-current (SI) memory cells suitable for high-speed digital communication circuits are introduced. A kind of novel BiNMOS technology is introduced in the first switched-current memory cell, and a high-speed fully differential BiCMOS structure is introduced in the second switched-current memory cell. Besides, measures of deducing the delay time formulae, optimum seeking the Parameters,...
A kind of novel CMOS optically coupled isolation amplifier (OCIA) composed of two operational amplifiers (OAs) is present. To improve the linearity and reduce the power consumption, the negative feedback signal is introduced to the input loop through two photoelectric coupled devices. Besides, other improvement actions are taken in this amplifier. Experimental results show that compared with the BiCMOS...
In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced...
In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the...
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage swing (LVS) logic, CMDL uses a shunt resistor at the differential output to obtain constant low swing signal without the need to reset low. Furthermore, conditional shunt transistors are used for the internal nodes to prevent...
As semiconductor process technologies scale down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization and delay2-power minimization. We show how various design criteria influence interconnect performance:...
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