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For a limited solder volume interconnect structure, bump interconnect reliability is more sensitive to the growth behavior of the interfacial intermetallic compounds(IMCs). The study of the effect of solder cap thickness on the interfacial diffusion reaction is of great importance to the application of copper pillar bump. Here, we investigated the effect of different solder cap thicknesses on IMCs...
With the strength of fine pitch, high electrical conductivity and excellent reliability, copper pillar interconnect becomes a promising alternative to traditional solder bump. However, bad surface smoothness is a severe problem and significantly affects the reliability of the bump connection. In this paper, numerical simulations on the shape evolution of copper pillar bump and the effect of bump dimension...
As the electronic packaging density continues to increase, flip chip or stacked packaging via bump bonding is gradually replacing traditional wire bonding and will become the mainstream packaging form in the future. For copper bumps, this new type of electronic interconnection has not yet been fixed by industry standards. Therefore, this paper has made a preliminary study on the reliability of this...
Copper pillar bump interconnect technology, with its good electrical properties and electromigration resistance, is becoming the next key technology for fine pitch interconnection of chips. The study of the effect of copper pillar bump size on the interfacial diffusion reaction has directive significance to the application of copper pillar bump. This paper focuses on the effect of size on the reliability...
As the demand expanding for high electrical performance, high pin count and low cost, the copper pillar bump packaging has been extensively used in recent years. However, the drawback is that copper pillar bump can introduce high stress, especially on low-k chip. In this paper, finite element method was adopted to optimize the structure of copper pillar bump, aiming at relieving the stress of low-k...
For years the substrate industry has been using SOP (solder on pad) to increase the reliability of flip chip packaging, because SOP is formed by the reflow of solder paste printed on the Cu pad of substrate, and this ensure the largest contact area of Cu pad and SOP. When a flip chip with solder balls is attached on top of a substrate and then they go through reflow process, the solder ball and SOP...
The thermal-mechanical reliability of the flip-chip with copper pillar bump is analyzed through finite element numerical simulation and Kriging response surface models optimization method. The results show that: the successive order of factors affecting the chip warpage is: die thickness, bump pitch, die thickness, substrate thickness, Cu Pillar height, Cu Pillar height, PI thickness, PI opening size;...
This work analyzes the electrical performance for three different packaging types applied on power management IC (PMIC) using a high efficiency dual-mode DC-DC buck converter. A 600 mA with 93 % efficiency dual-mode DC-DC buck converter is designed and fabricated by TSMC 0.35-µm CMOS process. The chip area is smaller about 2.1 mm2. The packaging parasitic effects of advanced single sided substrates...
Temporary bonding and release processes are regarded as the critical technologies in 2.5D and 3D IC integration. The process is especially challenging when the device contains high topography structures like copper pillar bumps. This paper presents the results of simulation, bumping process, wafer temporary bonding, thinning and debonding. Through careful consideration and optimization of the above...
With the miniaturization, multifunction, high speed development of the chip and package, the requirements for package substrate and 3D packaging becomes higher. As the IC line size continues to decrease, the signal transmission rate continues to improve and the amount and density of pin is getting more and more, the Pad pitch of package substrate which connects to it must be smaller and smaller. The...
With the miniaturization, multifunction, high speed development of the chip and package, the requirements for package substrate and 3D packaging becomes higher. As the IC line size continues to decrease, the signal transmission rate continues to improve and the amount and density of pin is getting more and more, the Pad pitch of package substrate which connects to it must be smaller and smaller. The...
Temporary bonding and release processes are regarded as the critical technologies in 2.5D and 3D IC integration. The process is especially challenging when the device contains high topography structures like copper pillar bumps. This paper presents the results of simulation, bumping process, wafer temporary bonding, thinning and debonding. Through careful consideration and optimization of the above...
When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy)...
The intermetallic compound (IMC) growths of Cu pillar bump with shallow solder (thin Sn thickness) were investigated during annealing or current stressing condition. After reflow, only Cu6Sn5 was observed, but Cu3Sn formed and grew at Cu pillar/Cu6Sn5 interface with increasing annealing and current stressing time. The kinetics of IMC growth changed when all Sn in Cu pillar bump was exhausted. The...
Copper pillars have been adopted and implemented in high volume manufacturing environment as early as 2006 as a replacement for high lead bumps. It is not only lead-free, but also offers the added advantage of higher stand-off, finer pitch capability and better electromigration resistance compared to tin-lead solder bumps. Owing to its significant superior thermal and electrical properties, higher...
Cu pillar bumps with eutectic SnPb solder were annealed and their microstructures were investigated. Linear relationship was observed between thickness of intermetallic compounds (IMCs: Cu6Sn5, Cu3Sn) and square root of time at 120 and 150degC. Kirkendall voids, formed by the diffusivity differences between Cu and Sn, were observed near the interface between Cu and Cu3Sn. There was a change in slope...
Cu pillar bump with eutectic SnPb was annealed and the micro structures were observed by scanning electron microscopy. Both of Cu6Sn5 and Cu3Sn grew following parabolic rate law at 120 and 150degC. At 165degC, Cu6Sn5 growth was stagnated while Cu3Sn growth rate was increased after 160 hour when all Sn was consumed. Kirkendall void was formed because of different diffusivities of Cu and Sn. The activation...
A flip-chip packaged two-dimensional (2-D) thermal flow sensor fabricated in CMOS technology is presented. The sensor consists of polysilicon resistor heaters, Al/polysilicon thermopiles, and a substrate bipolar transistor located in the center of the sensor chip. The thermopiles and the transistor were used to measure the change of the flow-induced temperature distribution on the flow-sensing surface...
In this paper, we will discuss the copper pillar bump structure and comparison will be made with standard solder bump and its advantages. Temperature cycles and high temperature storage reliability on QFN using copper pillar bump were performed. Results show that copper pillar bump can withstand up to 5000 cycles of mechanical stress test without mechanical and electrical failure. Electrical performance...
A flip-chip packaged thermal flow sensor is presented. The sensor chip was fabricated by standard CMOS technology and it consists of polysilicon resistor heaters, Al/polysilicon thermopiles and a substrate bipolar transistor in the center of the sensor chip. The sensor chip was flip-chip packaged on a thin ceramic substrate using copper pillar bump technology. Heat transfer is performed between the...
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