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True Random Number Generator (TRNG) occupies a commendable position in various information security applications. Random numbers are the one which need to possess the properties of uniform distribution and statically independent. Diffused bit Generator (DBG) is a reliable entropy source and core component to produce the sequence of random bits. The bits emanating from DBG is usually further sampled...
True random numbers have a fair role in modern digital transactions. In order to achieve secured authentication, true random numbers are generated as security keys which are highly unpredictable and non-repetitive. True random number generators are used mainly in the field of cryptography to generate random cryptographic keys for secure data transmission. The proposed work aims at the generation of...
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 μm, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality...
In digital signal processing the speed of the processor is dependent on the processing speed of a multiplier used in it, which affects total processing of a circuit. Hence, when a normal multipliers are used they consumes most of the power also gives rise to a delay. So to overcome this problems the high speed digital multiplier used nowadays. This paper introduced a low power booth multiplier, which...
Analog to Digital Converter (ADC) is an essential part of a mixed signal circuit design, which acts as a bridge between naturally occurring analog signals and digital signals. It has been a continuous effort of the researchers to reduce or keep the noise constant along with the level of advancement made in the field of mixed signal circuit design to increase the speed. This work has been intended...
This paper presents the Application Specific Integrated Circuit (ASIC) design of a Digital Pulse Width Modulation (DPWM) signal generator, for the implementation of PWM control signal generator, to be integrated on a single die with the single-stage input-powered bridge rectifier with boost switch (BRBS) DC boost converter, in view to eliminate the need of external PWM control signal generator, while...
This paper presents topological constraints of gate-level circuits obtained through standard cell recognition applied to gate-level commercial microelectronics verification. A suite of topological constraints, including the gate vertex count, net vertex count, terminal count, blocks, circuit genus, Euler characteristic, and number of faces are extracted from gate-level circuits obtained through standard...
Subthreshold source coupled logic circuits (STSCL) are normally used for designing ultra-low power components and systems operating in the weak inversion (subthreshold) regime. This paper presents an implementation of a robust source coupled technique i.e. Dynamic threshold source coupled logic (DTSCL) with push pull amplifier at the output stage. The proposed circuit was analyzed to obtain minimum...
This paper presents a novel design which compares a stream of digital data with a threshold value and accumulates the number of occurrences for when the data is above, equal to or below the threshold. The design is implemented using two transistor technologies viz. carbon nanotube (CNT) FETs (CNTFETs) and 32nm CMOS technology in order to shed light on the advantages of using CNTFETs over bulk-silicon...
Single-hop non-blocking networks have the advantage of providing uniform latency and throughput, which is important for cache-coherent many-core systems. This paper focuses on high performance circuit designs of multi-stage non-blocking networks as alternatives to crossbars. Existing work shows that Benes networks have much lower transistor count and smaller circuit area but longer delay than crossbars...
This paper present Static Random Access Memory (SRAM) cell with minimum number of transistor. A conventional SRAM cell requires 6 transistors having two nodes contains normal and complimented data. The scaling of CMOS technology has significant impacts on working of SRAM cell. In 4T cell reading and writing has been performed by each node separately [1]. In this paper SRAM cell (2T) designed and comparison...
The prime motive of this paper is to present the ternary logic as an alternative to binary logic as it is simpler and more energy efficient because the number of gates required will be reduced using ternary logic. Also Carbon nanotube field effect transistors (CNTFET) are used to further upgrade the novel nature of the designs in this paper. The simulation results using Cadence Virtuoso reported that...
The voltage controlled oscillator (VCO) is the core factor of Phase locked loop (PLL) oscillation frequency synthesizes, which is mainly used in modern electronics information processing systems. Multi stages VCO ring provide less oscillation frequency and high phase noise, so the single-stage source overcomes these problems. This paper presents a comparison between leakage power Reduction techniques...
One DFT solution for systems on chip, based on IDDQ measuring concept is presented in this paper. The application of Reconfigurable neurai networks off chip enables also good diagnostics capabilities. The solution is to be implemented in few digital blocks of the tree phase power meter IC and realized using CMOS035 technology. The simulation results obtained using Cadence Virtuoso show good performances...
An alternative CMOS manufacturing process architecture for implementing power integrated circuits that may be used for applications requiring a bridge topology is presented. A RESURF N-LDMOS high-side compatible power transistor was designed onto the new process using TSuprem4 and Medici TCAD software. Masks were designed using Cadence Virtuoso and the new structure was manufactured at X-Fab UK Ltd...
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