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The implemented ASICs, intended for mobile terminal usage, comprise a wideband high capacity OFDM direct conversion transceiver front-end for beyond 3G cellular systems. The transceiver operates with 83.2 MHz signal bandwidth and is designed for the operational frequency range of 5.15-5.725 GHz. The receiver and transmitter chips were fabricated with 0.13mum BiCMOS technology.
This paper presents a broadband very low 3rd-order intermodulation inductor-less low-noise amplifier (LNA) implemented in 0.13 mum CMOS technology. The LNA consists of a common-gate input stage for wideband impedance matching, followed by two parallel common source amplifiers which perform noise and distortion cancellation. Third-order distortion due to amplifier's second-order interaction is further...
A 15 to 18-GHz frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 15.3 to 18 GHz. The measured RMS phase noise of the synthesizer is 0.9deg (1 MHz...
This paper presents a voltage-controlled oscillator (VCO) with low phase noise by employing the CMOS field-plate (FP) transistors. The proposed FP transistors perform the improvement in flicker noise (1/f noise) was demonstrated in our previous investigation. A complete large-signal model for FP transistors was established by modified BSIM4 model with lossy substrate networks. The proposed 12-GHz...
Range reduction is important in evaluating trigonometric functions but not enough work is done in relation to the hardware implementation of it. A hardware floating point range reduction implementation is presented. The whole reduction is divided into two steps; the first is based on double-residue modular range reduction method and the second adopts on a novel method described in this paper. The...
A high precision 16-bit readout circuit for gas sensor interface is realized in 0.13μm CMOS technology. The front end signal conditioning circuit comprises a low power resistance-to-time period converter with subthreshold operation of transistors. The time-period proportional to the transducer output is digitized using a counter based frequency-to-digital conversion (FDC) technique. In order to handle...
A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (≫250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance...
The integration of millimeter-wave transceivers in CMOS technology can benefit from sophisticated signal processing and calibration techniques already is use at lower frequencies. This paper describes a CMOS heterodyne receiver with on-chip LO and frequency divider that achieves a noise figure of 6.9-8.3 dB while consuming 80 mW. A frequency divider is also presented that operates from 64 to 70 GHz...
A stereo 20-bit sigma-delta D/A primarily intend for audio applications is described in this paper. Mixed-radix number representation algorithms and high efficiency hardware realization method are used to dramatically reduce the area of the interpolation filter. Semi-digital current-mode filter is used as the reconstruction filter to achieve high dynamic range under the low power conditions. The proposed...
This paper presents the design of a dual-band L1/L2 global positioning system (GPS) receiver. A low-IF architecture was used for dual-band operation with analog on-chip image rejection. The receiver is composed of dual-band LNAs and down-conversion mixers, a complex variable-gain channel select filter, analog AGC loop, and a 2-bit analog-to-digital converter. The receiver is to be integrated with...
An 8-bit successive approximation analog-to-digital converter (ADC) with offset correction circuitry is presented for implantable sensor applications. The ADC is designed in a 0.13mum CMOS process technology and operates with voltage supplies down to 0.35 V using MOSFETs operating in their sub-threshold region of operation. Sample rates of 60kS/s are achieved with an INL and DNL of approximately 0...
A novel current source architecture is presented operating at 1.2 V for low power applications. The source has improved temperature compensation with respect to reported works. The circuit has been designed and fabricated in a 0.13mum ultra low power CMOS technology. The output current is 1 muA with measured variations less than 20 nA from RT up to 70degC.
A differential LC VCO is presented for commercial quad-band GSM/GPRS/EDGE applications. The VCO is designed in 0.13 mum CMOS process and meets stringent phase noise specifications. A technique to minimize the VCO gain variation is presented which reduces the Kvco variation to plusmn14%; more than three times smaller than the previous solutions. This technique results in reduction of the delay mismatch...
A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.
We investigate the effects of introducing a flexible interconnect into an exposed datapath. We define an exposed datapath as a traditional GPP datapath that has its normal control removed, leading to the exposure of a wide control word. For an FFT benchmark, the introduction of a flexible interconnects reduces the total execution time by 16%. Compared to a traditional GPP, the execution time for an...
A DLL featuring jitter-reduction techniques for a noisy environment is described. Loop behavior is controlled by monitoring the amount of jitter caused by supply noise of a replica delay line. The DLL is implemented in a 0.13mum CMOS process, and at 1 GHz, it has 4.58psrms jitter and 29pspp jitter with noisy replica delay line.
An interface ASIC for a capacitive 3-axis micro-accelerometer is implemented in a 0.13μm CMOS process. Die area and power dissipation are reduced by using time-multiplexed sampling and duty cycles down to 0.3%. The chip with 0.51 mm2 active area draws 62μA from a 1.8V supply while sampling 4 proof masses, each at 1 kS/s. With a plusmn4g capacitive 3-axis accelerometer, the measured noise in the x,...
A fully integrated 24GHz 4-channel phased-array transceiver in 0.13μm CMOS is reported. The architecture is based on a variable-phase ring oscillator in a PLL that modulates the baseband for each antenna in the TX mode and downconverts the received signal from all antennas in the RX mode without using RF mixers, signal-path phase shifters, or any power combining network. The 2.3 × 2.1 mm2 chip achieves...
A 4-wavelength DWDM optoelectronic transceiver, implemented in a 0.13mum CMOS SOI process, achieves an aggregate rate of 40Gb/s transmission over single fiber. The four channel WDM chip, operating all four Txs and Rxs in WDM configuration consumes -3.5W. This is at nominal operating conditions.
An experimental 512kB embedded PCM uses a current-saving architecture in a 0.13μm 1.5V CMOS. The write scheme features a low-write-current resistive device and achieves 416kB/s write-throughput at 100muA cell current. A charge-transfer direct-sense scheme has a 16b parallel read access time of 9.9ns in an array drawing 280μA. A standby voltage scheme suppresses leakage current in the cell current...
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