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Analog-to-Digital Converter (ADC) technology has been advancing to achieve a balance between speeds, size and cost. Successive approximation register (SAR) ADC is very popular for medium-to-high resolution as it is small but has difficulties in achieving high speed while flash ADC is big and not cost effective. Also, for different purposes, ADC have different resolution requirement. Producing ADCs...
The paper presents an improved analog-to-digital converter (ADC) architecture based upon traditional successive approximation register (SAR) type ADC concepts. The most important aspect of the present design is that it resolves two or more bits in a single cycle and hence requires much lesser time than a conventional SAR ADC for conversion of same resolution. A 12-bit, 3-bit per cycle ADC logic was...
A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller,...
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