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A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller,...
A threshold configuring SAR A/D converter is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. Low power and small area are achieved via a fully dynamic configurable comparator and an asynchronous controller with no need for capacitor-based feedback D/A converter. A 6-bit prototype in 90-nm digital CMOS technology achieves 32-dB SNDR at...
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