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Synchronous rectification (SR) has been extensively implemented in low-voltage switched-mode power conversion applications to reduce diode conduction losses. This paper addresses SR at higher voltages where the reverse recovery behaviour of the SR MOSFET's intrinsic diode is particularly challenging. A saturable inductor switching-aid circuit is introduced into a power converter in conjunction with...
Pre-congestion notification (PCN) defines admissible rates (AR) and supportable rates (SR) per link and marks the PCN traffic rate above these thresholds as AR- or SR-overload. The IETF standardizes simple mechanisms for admission control (AC) and flow termination (FT) based on this PCN-feedback for high-priority DiffServ traffic. While admission control (AC) has been extensively discussed in the...
This paper proposed a novel control scheme for soft switching flyback converter with synchronous rectification. By only adjusting the driver signal of the primary and secondary synchronous switches with the proposed control scheme, ZVS could be realized both at low and high input within 90 V-265 V AC at any load line. Stead-state operation waveforms and equivalent circuits has been presented in detail,...
This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture...
This paper describes a clock interface suitable in the high speed monolithic bipolar A/D converters. It is based on two main cells. An input buffer drives in a fully symmetrical manner capacitive loads with an optimal slew rate. Then, an adjustable delay circuit gives flexibility in the delay matching around the circuit. This interface implemented in a 7 Ghz bipolar process drives capacitive loads...
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