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Single ended data sensing for asymmetrical low voltage memories has become a topic of much interest due to its application in very low energy computing and communication. In this paper, we present an ultra-high-speed (UHS) data sensing scheme for single ended near threshold asymmetric static random access memory (SRAM) design in a 45nm standard CMOS process. The proposed bit-line decoupled single...
High variability in nano-scaled technologies can easily disturb the stability of a carefully designed standard 6T-SRAM cell, causing access failures during a read/write operation. We propose a 7T-SRAM cell to increase the read/write stability under large variations. The proposed design uses a low overhead read/write assist circuitry to increase the noise immunity. Use of an additional transistor and...
We present a novel power-aware yield enhancement design methodology and reconfiguration scheme for deep submicron SRAM designs. We show that with the continued trend of raising array supply to counter process variations, it is more effective to use a per-element selectable virtual power-supply scenario as opposed to single array supply with traditional redundancy schemes. The element can be a bank,...
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