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LTE-M, which is an abbreviated version of LTE-MTC(Machine Type Communication) can be said to have a variety of applications, including a large number of heterogeneous interconnection of large-scale network equipment. One of the most prominent problems is that the machines may have a large amount of access requests in a short time, which can easily lead to network congestion. At present, the contention-based...
In recent trends of VLSI technology the reversible logic has became the major area of research in optimization of area, power and speed constraints. The reversible logic has equal number of inputs and outputs. In wireless communications Viterbi algorithm is employed to have minimal number of communication channels. The Viterbi decoder design at 65nm technology using reversible logic has made an attempt...
Energy consumption is a major concern in today's wireless communications due to the consensus for a greener world. LTE-Advanced (LTE-A) has been standardized for the fourth-generation mobile communications to meet the growing demands for high-speed wireless communications. However, high-speed signal processing on LTE/LTE-A user equipment (UE) causes excessive power consumption. The discontinuous reception...
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
Embedded systems have become very important in our life; they pervade all fields in today's advanced technology. With the increasing importance of these systems, designers need to estimate the performance metrics such as Delay which includes processing and communication and Power consumption. This procedure is very critical and even crucial at an early stage of design and implementation. Using GPUs...
The performance of the DSP applications mainly depends on the multiplier, because the multiplication requires more iterations, long time and large area of the system than other computations. Hence to improve the performance of the system it is required to have high speed and low power consumption multiplier. In this paper we proposed the comparative study of two different algorithms, first one is...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application...
In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace...
Digital Signal Processor (DSP) as well as other microcontroller applications requires fast and low power consumption systems to compete with the advanced technology. The performance of the DSP applications mainly depends on the multiplier, because the multiplication requires more iterations, long time and large area of the system than other computations. Hence to improve the performance of the system...
Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino...
Approximate computing involves selectively reducing the number of transistors in a circuit to improve energy savings. Energy savings may be achieved at the cost of reduced accuracy for signal processing applications whereby constituent adder and multiplier circuits need not generate a precise output. Since the performance versus energy savings landscape is complex, we investigate the acceleration...
Comparator is basic building block for designing of the present analog and mixed signal (AMS) systems. Speed and Power are two major factors which are essential for high speed applications. In this paper, we present the analysis of existing clocked regenerative comparators in terms of power, speed and slew rate. A new clocked regenerative comparator is with domino logic proposed which exhibitsbetter...
The rapid growth in CMOS technology with the shrinking device size towards 22 nm has allowed for placement of billions of transistors on a single microprocessor chip. To achieve very high system performance, domino logic styles are widely employed in high performance VLSI chips together with aggressive technology scaling. Comparators are widely used in central processing units (CPUs) and microcontrollers...
The power consumption is a major concern for emerging applications like mobile phones, digital cameras, pace makers and multimedia processors. The power consumption can decreases by number of ways. The multiple supply voltage design is a dominant technique for the reduction of power consumption in System on Chips/Cores. The System on Chips /Cores uses level shifters and the level shifter will become...
This paper presents designs and analysis of n-to-2n — lines decoders created using fast and efficient method. Thanks to especially designed building blocks a decoder of any size can be built in easy way. Layouts of all needed fundamental blocks were designed in UMC 180 CMOS technology, as standard cells. A few layouts of decoders were designed as one and multi-level structures and their parameters...
Due to increased demand of portable and battery operated devices, ultra-low power and high speed devices with less area requirement are vital nowadays. Latch is the basic element for all the sequential circuits. This research paper proposes a 5-transistor level sensitive flip-flop and comparison results with the existing design are presented. Proposed and existing designs are paralleled in 32nm and...
In this paper, a novel adaptive TDMA-based clustering for critical event detection in Wireless Sensor Networks (WSN) is proposed. The aim of our adaptive approach is to detect the critical event, such a fire detection in the forest, at the required delay with minimum energy consumption. So, when an event occurs, only the sensor nodes in the detection area will be in active mode, while the others will...
This paper enumerates the design of high speed Positive & Negative edge triggered D flip flops using AlGaAs/GaAs MODFET. This Flip Flops having less number of transistors. It can be efficiently used in VLSI ICs. The verification is done using simulation the proposed Flip Flops appear to have better speed of operation. It is simple and suitable to SPICE simulation of hybrid digital ICs.
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
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