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This paper analyzes the behavior of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that...
We have proposed a method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminal. The method can assign a known logic value to a fault location automatically by applying a ramp voltage and as a result, it requires only one test vector to detect a fault as a delay fault or an erroneous logic value at primary outputs. In this paper,...
The paper addresses here the fault model of particular type of manufacturing defects in the metal layers of deep sub-micron (DSM) chips, e.g. conductive particle contamination, bad handling or under-etching defects in the pair of parallel interconnects which lead to both severe non-zero resistive bridging fault and increased crosstalk coupling fault between the on-chip aggressor-victim interconnects...
Detection of killer defects is critical to improving yields in VLSI fabrication. Bright and dark-field inspection tools detect both killer and non-killer defects, and in some cases a high level of nuisance defects may adversely affect the ability to monitor and eliminate the real ones that have a detrimental impact on device yield. E-beam inspection tools take advantage of a phenomenon referred to...
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