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This work proposes the construction of a tool for communication between listeners and speakers through the Brazilian Sign Language (LIBRAS) and the French Sign Language (LFS), making a simultaneous translation between the Brazilian written language and the French written language integrated through a web application, with the aid of the recognition of signals by techniques of image recognition and...
The paper deals with the development of specific/proprietary communication protocol for generic embedded modular control system which is based on high-speed serial communication lines. The author also describes the design and the implementation of efficient communication stack for an FPGA device. The designed protocol/stack enables an effective high speed transfer of data between master and slave...
The dual-port RAM based on FPGA plays an important role in the design of complex system. This paper firstly introduces the basic characteristics of reset, enable, read and write dual-port RAM, and their effects for the system's reliability, real-time and power consumption. And then focus on the dual-port RAM to achieve a large-capacity shift caches and the dual-port RAM array of communications chain...
Ensuring network traffic privacy and improved performance is a key factor to provide trustworthy communication for data transmission. In this research work, we investigate a mechanism to integrate our previous works: open TCP/IP core and the cryptosystem on the same Field-Programmable Gate Array (FPGA) chip. Challenges are addressed in this paper regarding the data format of the encrypted message...
Underwater acoustic modems are normally considered to offer low data-rates over distances of a few kilometers. This paper reports on open water performance of a high-frequency acoustic modem with demonstrated data rates of 380 kbps. The modem is simple and runs on commodity hardware using well understood signaling techniques.
The energy in FPGA computations can be dominated by data communication energy, either in the form of memory references or data movement on interconnect (e.g., over 75% of energy for single processor Gaussian Mixture Modeling, Window Filtering, and FFT). In this paper, we explore how to use data placement and parallelism to reduce communication energy. We further introduce a new architecture for embedded...
Applications in areas such as telehealth and household security often require wireless communication between low-power embedded systems and personal smartphones. This paper presents the design and implementation of a project that exploits Bluetooth capabilities in smartphones running the Android Operating System to communicate wirelessly in real-time with an FPGA-based embedded system. The use of...
This paper aims at introducing a methodology that allows an easy implementation of IP_Cores focusing only on their functionalities rather than their interfaces and their integration in a given architecture. The proposed approach implements all the communication infrastructure needed by a component described in VHDL, to be finally inserted into a real architecture that can be implemented on FPGAs,...
Underwater acoustic links have low capacity because that operate at low frequencies. These low frequencies are used because they allow long range communication. Networks allow short range links to provide long range communication, eliminating the need for these long link ranges. Therefore high frequencies can be used for underwater acoustic communication. Such high-frequency underwater acoustic communication...
This paper describes how small, low-cost robots can be used in practical assignments in different programming modules, both for high- and low level programming, and both at undergraduate as well as graduate level. The constructed robots described here are designed to have a diverse use in different type of exercises. The design utilises both an ARM processor used for running a Java virtual machine...
This paper presents a DSP/FPGA based multi-sensory flexible-joint robot including modular mechanics, hardware and software architecture. The robot is composed of four modular flexible joints and a DLR-HIT-Hand. In each joint there is a Field Programmable Gate Array (FPGA) for sensor data processing, brushless DC motor control and communication. The kernel of the hardware system is a PCI-based high...
Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design problem due to the limited number of available pins (in not Ball Grid Array package) and to the common need of a frequency reduction, especially into systems that require an external System on Programmable Chip (SoPC). In this paper, an ASIC solution based on bi-synchronous FIFO structures for frequency...
The approach described in this paper uses an array of Field Programmable Gate Array (FPGA) devices to implement a fault tolerant hardware system that can be compared to the running of fault tolerant software on a traditional processor. Fault tolerance is achieved is achieved by using FPGA with on the fly partial programmability feature. Major considerations while mapping to the FPGA includes the size...
Making use of rich inner resource of FPGA(field programmable gate arrays), a wireless alarm sending system is designed. It includes encoder, FSK(frequency shift keying) modulation and every channelpsilas control circuits, which can decrease volume and increase reliability of the alarm system. The demodulation of receive system is realized by an application specific integrated circuits MC3372. With...
This paper presents a network-on-chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System.-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers...
This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800...
The following topics are dealt with: field programmable logic; design tools and compilers; multicore systems; high performance computing; run-time support; placement and routing; biology applications; power; communication and security; architecture; image and video processing; and network on chip.
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