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The predictability of execution qualities including timeliness, power consumption, and fault-tolerability is of utmost importance for the successful introduction of multi-core architectures in embedded systems requiring guarantees rather than best effort behavior. Examples are real-time and/or safety-critical parallel applications. In particular for future many-core architectures, analysis tools for...
This paper presents a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with 60.9 dB SNDR at 50MS/s while with 41.3uW power consumption. Several techniques were used to decrease the power consumption. First, Segmented architecture was used to decrease the total number of capacitance. Aligned switching with skip (ASS) method was used during copy MSB bits from coarse to...
The successive-approximation-register (SAR) analog-to-digital converter (ADC) has recently attracted a lot of interest due to its power efficiency as well as its simple structure. The main challenge with this type of ADC is the limited sampling rate which is due to its sequential operation. In flash-SAR architectures, this problem is mitigated by cascading flash and SAR ADCs which operate in two consecutive...
In this paper, the conventional single-stage latched comparator is improved for both high speed and low noise flash ADCs. In the proposed method for high-speed applications, the common mode level of output voltage is preserved unchanged during both amplification and latch operations, to speed up the comparison of small voltage differences. Also, the amplitude of digital control signals is reduced...
SoC designers typically use a processor simulator to generate a memory trace and apply the generated trace to a memory simulator in order to collect the performance statistics of a complete system. This is an inaccurate process for most applications, making it difficult to optimize the processor and memory configurations. In this paper, we study the problems encountered in the typical simulation approach...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
In this paper, we address the issue of transmission power control (TPC) in wireless ad hoc networks. Power control plays an important role in energy saving and network performance enhancement. However, the existing TPC schemes either face the problem of hidden and exposed terminal or have additional hardware requirements. We propose a novel distributed power control protocol, called Receiver Initiated...
Correlative minimum shift keying (MSK), a second order polynomial modulation scheme known as tamed frequency modulation (TFM), is a constant envelope type of modulation with a perfect peak to average power ratio (PAPR), besides the property of low out of band power. We apply the linearized TFM to the single carrier transmission with frequency domain equalization (SC/FDE) concept. We then obtain a...
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