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For multi-channel high-speed image data of certain space remote sensing camera, this paper proposed a new image data acquisition and storage system. First of all, the system uses Field-Programmable Gate Array(FPGA) controlling synchronous dynamic random access memory(SDRAM) array to realize the cache of image data, then according to the received commands, sends certain channel's image data to the...
In this paper we introduce the implementation of a block-LDPC codec on FPGA with simulation. The result shows that this codec is suitable for block LDPC with less resource consumption.
This paper designs a Flash controller, which helps the FPGA main state-machine to manage a Flash memory chip efficiently. The controller builds its own instruction set. User operates the proposed controller with the system clock of FPGA without caring about the timing sequences required by the Flash. The proposed Flash controller develops its own method for the reorganization and mapping of invalid...
One I2C protocol design method for reusability was proposed. In this method, design was divided into 3 levels: protocol level, signal level and interface level. Protocol level can be reused without any modification. Signal level can be reused by setting the number of be transferred byte according to specific operation. Interface level can be reused by changing the number of operation mode and the...
This paper presents a scalable design and verification methodology for FPGA-based motor drives for aircraft application, working at high-temperature environment. ProASICPlus from Actel Family (0.22 μm digital CMOS 4 Layer Metal Flash-Based CMOS Process) was chosen to implement the studied motor drive which consists on a current control. The design is implemented at a frequency of 24 MHz and junction...
The paper designs a driving circuit of high sensitive, wide dynamic for CCD sensing imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Field Programmable Gate Array (FPGA) is used as the main detechniquevice to accomplish the timing design of the circuits and power driver control of the sensor. By using the Correlated Double Sampling (CDS) technique,...
Today's machine automation systems are demanding for better throughput, faster response, built in safety features and high speed communication support, besides satisfying IEC61131-3 control specification. MEMS sensors & actuators along with increased control logic complexities are stretching limits of conventional Programmable Logic controllers (PLCs) generally used for industrial and high end...
An SoC framework is presented, comprising of a plug-and-play infrastructure where the system communication is abstracted from the processing elements. A software scheduler is used with a hardware modelling environment for latency analysis. Using the framework, an LTE uplink data channel (PUSCH) receiver design is shown to meet the stringent latency targets.
Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one of the most important features in FPGA to support small size memory application and available anywhere across the chip. But the distributed memory is...
The data acquisition architecture for the tracking detector of the MECO experiment will consist of a preamplifier/discriminator feeding a buffered digitizer which will be controlled by programmed logic. The digitizer converts the timing and analog waveform into digital storage for later readout. In order to evaluate this conceptual design, a prototype system was assembled using an existing digitizer...
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