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Highly-ported memories are pervasive within superscalar processors. Accordingly, they have been targets for full-custom design using multi-ported versions of the 6T SRAM bitcell. Unfortunately, full-custom design of highly-ported memories is becoming exceedingly difficult in deep sub-micron technologies. This paper makes the case for implementing highly-ported memories with standard cells (flip-flops,...
Virtual channel communication is a commonly used technology in spacecraft to transfer platform engineering data and high speed scientific data from payloads such as synthetic aperture radar or hyper spectral camera. FIFO type buffer has been widely applied in virtual channel data transfer owing to its simple interface. But the control logic of FIFO can be disturbed by single event upset in space radiation...
In this paper, an approach is made to design a Thermal and Power efficient RAM for that reason we have used DDR4L memory and six different members of SSTL I/Os standards on 28nm technology. Every spacecraft requires most energy efficient electronic system and for that very purpose we have designed the most energy efficient RAM. In this design, we have taken two main parameters for analysis that is...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact product time-to-market. This paper introduces a new approach to evaluate, at early design phase, the reliability of a computing system running a software. The approach can be used when the hardware architecture is not completely defined...
In this work, we are going to use thermal aware approach in random access memory (RAM) design and also testing thermal stability by working on different ambient temperatures 285.15K, 288.15KC, 308.15C, 323.15K, 325.15K and 348.15K. We have observe the compatibility of our device with wireless network by working on different processor frequencies i.e. 1.2 GHz, 1.7 GHz, 2.5 GHz, 3 GHz and 3.6 GHz. There...
In this work of low power memory design on FPGA, we are using the most energy efficient I/O standard among LVCMOS, HSLVDCI, HSTL, LVDCI_DV2 and SSTL. I/O standard is used to match impedance of transmission line, impedance of port and impedance of memory for avoidance of transmission line reflection. In naming convention of I/O Standard, LV is Low Voltage, HS is High Speed, DV2 is Half Impedance, CMOS...
Star Sensor, also known as star-tracker, is a high-accuracy 3-axis attitude sensor used onboard spacecrafts. It processes stars from a sky image captured using an area imaging detector (generally 1k × 1k pixels Charge Coupled Device) to generate attitude information. Its accuracy about the boresight is poorer than about the cross-axes. This is improved by using two sensor heads with staggered Fields-Of-View...
Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing...
This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified...
After giving historical data on FDTD speed and problem sizes, the state of the art approach to fast and efficient FDTD simulations is explained for large scale structures. Future challenges include the simultaneous simulation of the RF device or antenna and its surrounding environment, increasing the modeling effort by at least an order of magnitude. An intelligent hierarchical concept exploiting...
In this paper, a signal acquisition system for continuous-wave lidar is present in two ways. One is the hardware design, the other is the device design and application program design using FPGA with USB2.0 interface. The sampling rate of this system is up to 300Msps. The signal correlation and accumulation is processed by using FPGA with 512M RAM The experimental results show that it can be used in...
The use of FPGA internal RAM can be an effective alternative to external FIFO, using the method OF Programming FOR the FPGA, Make full use of FPGA internal resources that provided strong support For the realization of a programmable system chip (SOPC, SystemOn Programable Chip). It Effected reducing the use of devices and minimizing the circuit boards. Acquisition and storage respectively controlled...
In this paper, we present a rate-compatible LDPC decoder architecture which supports code rates between the rate of the mother code and 1. The rate-1/2 2304-bit Quasi-Cyclic (QC) LDPC codes with dual-diagonal parity check structure is selected from WiMax standard as the mother code and is punctured using specific puncturing patterns to obtain arbitrary rates. Parallel layered decoding architecture...
This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is look-up table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using...
With the advance of VLSI technology, power consumption of chips has become a major concern in the state of art CMOS circuits design. Among all kinds of previous power analysis methods, the gate-level power analysis can give a relatively accurate result and has been commonly used. However, the simulation speed is very low due to large amount switching activity records for all gate-level cells. In this...
This paper proposes a novel, fast, highly-parallel and configurable architecture for zigzag scan and optional scans in multiple video coding standards, including H.261, MPEG-1,2,4, H.264/AVC, and AVS. Arbitrary scan patterns could be supported by configuring the ROM data, and the proposed architecture can largely reduce the processing cycles. This makes it possible to integrate the scan unit into...
Addressing both standby and active power is a major challenge in developing system-on-chip designs for battery-powered products. Powering off sections of logic or memories loses internal register and RAM states so designers have to weigh up the benefits and costs of implementing state retention on some or all of the power gated subsystems where state recovery has significant real-time or energy cost,...
In view of the need to examine the performance of seeding for corn precise seeder, a study has been carried on the interrupt examination with a timer to eight group pulse intervals the assembly language procedure algorithm and the hardware circuit, and realized in MCS-51 monolithic computer systems. This paper proposed the absolute-clock and the relative-clock's thought; has found a special time-constant,...
In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA The proposed RAM specification has been tested with different target devices.
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