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This paper presents a new slack-time based algorithm for dual Vdd design to achieve maximum energy saving. Although a global optimum is sought computation time is kept low. The slack of a gate is defined as the difference between the critical path delay for the circuit and the delay of the longest path through that gate. A linear-time algorithm is used for computing slacks for all gates of the circuit...
Power integrity gains growing importance for integrated circuits in 45nm technology and beyond. This paper provides a tutorial of modeling and design for beyond the die power integrity. We explain the background of simultaneous switching noise (SSN) and its impacts on circuit designs. We discuss various models of different accuracy and complexity for the board, package and chip, and suggest how to...
Signal and power integrity in electronic design is not an easy subject to teach as it involves both electrical circuit and electromagnetic field as well physical structure of active and passive components. Great effort has been made to develop teaching and evaluating materials for the subject in engineering schools, especially at undergraduate level. This paper describes our work on the development...
As the industry moves from single- to multicore processors, the challenges of how to reliably design and analyze power delivery for such systems also arise. We study various workload assignments to cores and their impact on the global power grid noise. We develop metrics to estimate the amount of noise propagated from core to core and propose a power supply noise aware workload assignment method....
We newly proposed a low-power and high-speed mobile display digital interface (MDDI) client receiver in this paper. The receiver was designed as a low-power circuit which had a constant current dissipation over variations of the common-mode voltage (VCM) and power supply voltage, and was able to operate at a rate of 450 Mbps or above under the conditions of a power supply of 3.3 V and a temperature...
A novel bandgap reference for minimizing current-mirror mismatch is presented. In the proposed circuit, the small-signal current variations in the two current paths are self-compensated while in the conventional bandgap core they are multiplied. As a result, error caused by current-mirror mismatch has been much reduced in the proposed circuit. Moreover, the voltage variations caused by temperature...
Although local biasing of components used in an analog circuit is shown to be a very attractive design methodology, significantly simplifying the design procedure (Hashemian, 2005), it makes the DC supplies distributed and often not in desire locations in the circuit. In response to this problem a new technique is developed that in conjunction with the local biasing it handles the DC supply sources...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
There have been many solutions to create a soft error immune SRAM cell. These solutions can be broken down into three categories: a) hardening, b) recovery, c) protection. Hardening techniques insert circuitry in an SRAM cell possibly duplicating the number of transistors. Recovery techniques insert current monitors in SRAMs to detect SEUs and they employ error correcting codes or redundancy to mitigate...
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