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In order to protect the internal circuit effectively, the design of ESD clamp protection circuit becomes more important. In this paper, a novel ESD power clamp circuit for 0.18 ??m CMOS process is proposed. The new clamp circuit uses the edge triggering TSPCL D flip-flop to turn on and time delay. By adding the leakage transistor of small size, the circuit can turn off effectively. It has the advantage...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultradeep submicron technologies under the influence...
This paper presents a 7th order polyphase (14th order bandpass) gm-C IF filter implemented in a 0.35 µm CMOS process. The filter bandwidth is 1 MHz, the center frequency is 3 MHz, the image band rejection is higher than 53 dB, the stop band attenuation is at least 40 dB, and the in-band group delay variation is 0.5 µs. The noise floor is 170 µVrmsand the spurious free dynamic range is at least 59...
CMOS technology scaling dictates the reduction of the Source/Drain (S/D) junction depths to reduce punch-through and short channel effects. But simultaneously, lower contact resistances are needed as the device channel resistance decreases low S/D junction sheet resistance is required for improved density, and low S/D junction leakage should be maintained for reduced stand-by power and longer refresh...
The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were obtained. Hot carrier degradation experiments showed that NMOS devices could operate at 2.5 V supply voltage. The delay per stage...
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